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公开(公告)号：US07968442B2
公开(公告)日：2011-06-28
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L21/28
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译： 翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。 鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。 形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过 栅电极。
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公开(公告)号：US20100109057A1
公开(公告)日：2010-05-06
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译： 翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。 鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。 形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过 栅电极。
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公开(公告)号：US08637407B2
公开(公告)日：2014-01-28
申请号：US13242504
申请日：2011-09-23
申请人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.
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4.发明授权Methods of fabricating integrated circuit devices that utilize doped poly-Si1−xGex conductive plugs as interconnects 有权使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法公开(公告)号：US07316954B2
公开(公告)日：2008-01-08
申请号：US10968233
申请日：2004-10-19
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该器件还包括在接触孔中延伸并且电连接到第一导电类型的半导体区域的第一导电类型的多晶Si-1-x-Ge
提供导电类型。 还提供了制造集成电路器件的相关方法。 -
公开(公告)号：US20100055914A1
公开(公告)日：2010-03-04
申请号：US12428963
申请日：2009-04-23
申请人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/308
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.
摘要翻译： 可以通过使用自对准反向图案化来同时形成多个掩模图案来提供形成半导体器件的方法，包括具有不同宽度的各个掩模图案元件。
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公开(公告)号：US20060246666A1
公开(公告)日：2006-11-02
申请号：US11410837
申请日：2006-04-26
申请人： Jeong-nam Han , Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi , Woo-gwan Shim , Hyo-san Lee , Chang-ki Hong , Sang-jun Choi
发明人： Jeong-nam Han , Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi , Woo-gwan Shim , Hyo-san Lee , Chang-ki Hong , Sang-jun Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.
摘要翻译： 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。
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7.发明申请Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects 有权使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法公开(公告)号：US20050064660A1
公开(公告)日：2005-03-24
申请号：US10968233
申请日：2004-10-19
IPC分类号： H01L21/283 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。 还提供了制造集成电路器件的相关方法。
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8.发明授权Integrated circuit devices that utilize doped Poly-Si1−xGex conductive plugs as interconnects 有权利用掺杂的Poly-Si1-xGex导电插头作为互连的集成电路器件公开(公告)号：US06828616B2
公开(公告)日：2004-12-07
申请号：US10012116
申请日：2001-11-13
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有与衬底表面相邻的第一导电类型的半导体区域。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。
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公开(公告)号：US06468924B2
公开(公告)日：2002-10-22
申请号：US09871430
申请日：2001-05-31
申请人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
发明人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
IPC分类号： H01L2131
CPC分类号： H01L21/0228 , C23C16/34 , C23C16/345 , C23C16/402 , C23C16/403 , C23C16/405 , C23C16/409 , C23C16/45531 , C23C16/45542 , H01L21/02164 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/02274 , H01L21/3185
摘要： Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.
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10.发明授权Semiconductor devices having narrow conductive line patterns and related methods of forming such semiconductor devices 有权具有窄导线图形的半导体器件和形成这种半导体器件的相关方法公开(公告)号：US08310055B2
公开(公告)日：2012-11-13
申请号：US12645820
申请日：2009-12-23
申请人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
发明人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L23/522 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.
摘要翻译： 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。
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