公开(公告)号：US06706142B2

公开(公告)日：2004-03-16

申请号：US09997158

申请日：2001-11-28

申请人： Stephen E. Savas ,  John Zajac ,  Mark J. Kushner ,  Ronald L. Kinder

发明人： Stephen E. Savas ,  John Zajac ,  Mark J. Kushner ,  Ronald L. Kinder

IPC分类号： C23C1600

CPC分类号： C23C16/505 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32623 ,  H01L21/3065 ,  H01L21/31116

摘要： Inductively-coupled plasma reactors for anisotropic and isotropic etching of a substrate, as well as chemical vapor deposition of a material onto a substrate. The reactor system comprises a processing chamber with a plasma shaping member contained therein. In one embodiment, the plasma shaping member extends from a portion of the top wall of the processing chamber, downward into the chamber, and it is generally positioned above the center of the substrate. The shaping member may be a separate piece of hardware attached to the top wall of the chamber, or it may be an integral part of the wall itself. Preferably, the plasma shaping member has a recessed portion in the middle and an extended portion located at a distance outside that of the recessed region. The plasma shaping member may be fabricated from virtually any material since it is at an electrically floating potential during processing of the substrate. The plasma shaping member serves to reduce the ion density in the middle of the chamber, above the center of the substrate, thereby enhancing the uniformity of the plasma throughout the chamber. The enhanced plasma uniformity in turn results in more uniform processing rates of a substrate.

摘要翻译： 感应耦合等离子体反应器，用于各向异性和各向同性蚀刻衬底，以及将材料化学气相沉积到衬底上。 反应器系统包括其中包含等离子体成形构件的处理室。 在一个实施例中，等离子体成形构件从处理室的顶壁的一部分向下延伸到室中，并且其通常位于衬底的中心的上方。 成形构件可以是附接到室的顶壁的单独的硬件件，或者其可以是壁本身的整体部分。 优选地，等离子体成形构件在中间具有凹陷部分和位于凹陷区域外侧的延伸部分。 等离子体成形构件可以由几乎任何材料制成，因为它在衬底的加工期间处于电浮动电位。 等离子体成形构件用于降低腔的中间的离子密度，在衬底的中心之上，从而增强整个腔室中等离子体的均匀性。 增强的等离子体均匀性又导致衬底的更均匀的处理速率。

公开(公告)号：US6133550A

公开(公告)日：2000-10-17

申请号：US140614

申请日：1998-08-26

申请人： Stewart K. Griffiths ,  Robert H. Nilson ,  Brad S. Mattson ,  Stephen E. Savas

发明人： Stewart K. Griffiths ,  Robert H. Nilson ,  Brad S. Mattson ,  Stephen E. Savas

IPC分类号： H01L21/677 ,  C23C16/46 ,  C23C16/54 ,  C30B25/10 ,  C30B31/12 ,  H01L21/00 ,  H01L21/205 ,  H01L21/26 ,  H01L21/265 ,  F27D11/00

CPC分类号： H01L21/67248 ,  C23C16/46 ,  C23C16/54 ,  C30B25/10 ,  C30B31/12 ,  H01L21/67109

摘要： An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

公开(公告)号：US5225024A

公开(公告)日：1993-07-06

申请号：US750720

申请日：1991-08-22

申请人： Peter R. Hanley ,  Stephen E. Savas ,  Karl B. Levy ,  Neeta Jha ,  Kevin Donohoe

发明人： Peter R. Hanley ,  Stephen E. Savas ,  Karl B. Levy ,  Neeta Jha ,  Kevin Donohoe

IPC分类号： H01J37/32 ,  H05H1/46

CPC分类号： H01J37/32623 ,  H01J37/3266 ,  H05H1/46

摘要： Magnetic confinement of electrons in a plasma reactor is effected using electro-magnetic coils and other magnets which generate respective magnetic fields which are mutually opposed and substantially orthogonal on their common axis to the major plane of a wafer being processed, instead of being aligned and parallel to the major plane as in prior magnetically enhanced plasma reactors. The respective magnetic fields combine to yield a net magnetic field which is nearly parallel to the wafer away from the magnetic axis so that electrons are confined in the usual manner. In addition, a magnetic mirror provides confinement near the magnetic axis. The E.times.B cross product defines a circumferential drift velocity urging electrons about a closed path about the magnetic axis. The magnetic and cross-product forces on plasma electrons have a rotational symmetry which enhances reaction uniformity across the wafer; this contrasts with the prior art in which lateral drift velocity disturbs plasma symmetry and thus reaction uniformity. Furthermore, the disclosed field geometry permits stronger electron confinement which enhances plasma reaction rates.

摘要翻译： 使用电磁线圈和其它磁体来实现等离子体反应器中的电子的限制，这些磁体产生各自的磁场，这些磁场在它们的公共轴线上相互对置并且基本上正交于被处理的晶片的主平面，而不是对准和平行 到现有的磁增强等离子体反应器中的主平面。 相应的磁场结合起来产生一个净磁场，该磁场几乎平行于离开磁轴的晶片，使得电子以通常的方式被限制。 此外，磁镜在磁轴附近提供约束。 ExB交叉乘积定义围绕磁轴围绕闭合路径推动电子的周向漂移速度。 等离子体电子的磁性和交叉积分力具有提高晶片反应均匀性的旋转对称性; 这与现有技术形成对比，其中横向漂移速度扰乱等离子体对称性并因此干扰反应均匀性。 此外，所公开的场几何形式允许更强的电子限制，这增强了等离子体反应速率。

公开(公告)号：US08413604B2

公开(公告)日：2013-04-09

申请号：US11564134

申请日：2006-11-28

申请人： Rene George ,  Andreas Kadavanich ,  Daniel J. Devine ,  Stephen E. Savas ,  John Zajac ,  Hongching Shan

发明人： Rene George ,  Andreas Kadavanich ,  Daniel J. Devine ,  Stephen E. Savas ,  John Zajac ,  Hongching Shan

IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/32431 ,  H01L21/02104 ,  H01L21/3065 ,  H01L21/6715 ,  H05H1/46

摘要： A more uniform plasma process is implemented for treating a treatment object using an inductively coupled plasma source which produces an asymmetric plasma density pattern at the treatment surface using a slotted electrostatic shield having uniformly spaced-apart slots. The slotted electrostatic shield is modified in a way which compensates for the asymmetric plasma density pattern to provide a modified plasma density pattern at the treatment surface. A more uniform radial plasma process is described in which an electrostatic shield arrangement is configured to replace a given electrostatic shield in a way which provides for producing a modified radial variation characteristic across the treatment surface. The inductively coupled plasma source defines an axis of symmetry and the electrostatic shield arrangement is configured to include a shape that extends through a range of radii relative to the axis of symmetry.

摘要翻译： 实施了更均匀的等离子体处理，以使用电感耦合等离子体源来处理处理对象，该等离子体源使用具有均匀间隔开的狭缝的开槽静电屏蔽件在处理表面处产生不对称等离子体密度图案。 槽式静电屏蔽以补偿不对称等离子体密度图案的方式进行修改，以在处理表面提供改良的等离子体密度图案。 描述了更均匀的径向等离子体处理，其中静电屏蔽装置被配置为以提供在整个处理表面上产生修改的径向变化特征的方式来替换给定的静电屏蔽。 电感耦合等离子体源限定对称轴，并且静电屏蔽装置被配置为包括相对于对称轴延伸穿过半径范围的形状。

公开(公告)号：US20100151694A1

公开(公告)日：2010-06-17

申请号：US12334425

申请日：2008-12-12

申请人： Bruce W. Peuse ,  Yaozhi Hu ,  Paul Janis Timans ,  Guangcai Xing ,  Wilfried Lerch ,  Sing-Pin Tay ,  Stephen E. Savas ,  Georg Roters ,  Zsolt Nenyei ,  Ashok Sinha

发明人： Bruce W. Peuse ,  Yaozhi Hu ,  Paul Janis Timans ,  Guangcai Xing ,  Wilfried Lerch ,  Sing-Pin Tay ,  Stephen E. Savas ,  Georg Roters ,  Zsolt Nenyei ,  Ashok Sinha

IPC分类号： H01L21/316 ,  C23C16/00

CPC分类号： H01L21/31654 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/68771

摘要： Plasma assisted low temperature radical oxidation is described. The oxidation is selective to metals or metal oxides that may be present in addition to the silicon being oxidized. Selectivity is achieved by proper selection of process parameters, mainly the ratio of H2 to O2 gas. The process window may be enlarged by injecting H2O steam into the plasma, thereby enabling oxidation of silicon in the presence of TiN and W, at relatively low temperatures. Selective oxidation is improved by the use of an apparatus having remote plasma and flowing radicals onto the substrate, but blocking ions from reaching the substrate.

摘要翻译： 描述了等离子体辅助低温自由基氧化。 除了被氧化的硅之外，氧化对于可能存在的金属或金属氧化物是选择性的。 选择性通过适当选择工艺参数来实现，主要是H2与O2气的比例。 可以通过将H 2 O蒸汽注入到等离子体中来扩大工艺窗口，从而可以在相对低的温度下在TiN和W的存在下氧化硅。 通过使用具有远离等离子体和流动基团的装置到衬底上但阻止离子到达衬底的装置来改善选择性氧化。

公开(公告)号：US20090028761A1

公开(公告)日：2009-01-29

申请号：US11829258

申请日：2007-07-27

申请人： Daniel J. Devine ,  Charles Crapuchettes ,  Dixit Desai ,  Rene George ,  Vincent C. Lee ,  Yuya Matsuda ,  Jonathan Mohn ,  Ryan M. Pakulski ,  Stephen E. Savas ,  Martin Zucker

发明人： Daniel J. Devine ,  Charles Crapuchettes ,  Dixit Desai ,  Rene George ,  Vincent C. Lee ,  Yuya Matsuda ,  Jonathan Mohn ,  Ryan M. Pakulski ,  Stephen E. Savas ,  Martin Zucker

IPC分类号： B01J19/08 ,  B23P17/04

CPC分类号： H01L21/6719 ,  H01L21/67069 ,  Y10T29/49

摘要： An apparatus and method are described for processing workpieces in a treatment process. A multi-wafer chamber defines a chamber interior including at least two processing stations within the chamber interior such that the processing stations share the chamber interior. Each processing station includes a plasma source and a workpiece pedestal for exposing one of the workpieces to the treatment process using a respective plasma source. The chamber includes an arrangement of one or more electrically conductive surfaces that are asymmetrically disposed about the workpiece at each processing station in a way which produces a given level of uniformity of the treatment process on a major surface of each workpiece. A shield arrangement provides an enhanced uniformity of exposure of the workpiece to the respective one of the plasma sources that is greater than the given level of uniformity that would be provided in an absence of the shield arrangement.

摘要翻译： 描述了用于在处理过程中处理工件的装置和方法。 多晶片室限定腔室内部，其包括腔室内部的至少两个处理站，使得处理站共享腔室内部。 每个处理站包括等离子体源和用于使用相应的等离子体源将工件中的一个暴露于处理过程的工件基座。 腔室包括一个或多个导电表面的布置，其以在每个加工工位上围绕工件不对称地设置，以在每个工件的主表面上产生给定水平的处理工艺的均匀性。 屏蔽装置提供了工件对等离子体源的相对一个的曝光增强的均匀性，其大于在没有屏蔽装置的情况下提供的给定的均匀度水平。

公开(公告)号：US06253704B1

公开(公告)日：2001-07-03

申请号：US09398553

申请日：1999-09-17

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： C23C1600

CPC分类号： H01J37/321 ,  H01J37/32082 ,  H01J37/32706 ,  H01J2237/004 ,  H01J2237/3345

摘要： Apparatus and method for an improved etch process. A power source alternates between high and low power cycles to produce and sustain a plasma discharge. Preferably, the high power cycles couple sufficient power into the plasma to produce a high density of ions (≳1011cm−3) for etching. Preferably, the low power cycles allow electrons to cool off to reduce the average random (thermal) electron velocity in the plasma. Preferably, the low power cycle is limited in duration as necessary to prevent excessive plasma loss to the walls or due to recombination of negative and positive ions. It is an advantage of these and other aspects of the present invention that average electron thermal velocity is reduced, so fewer electrons overcome the plasma sheath and accumulate on substrate or mask layer surfaces. A separate power source alternates between high and low power cycles to accelerate ions toward the substrate being etched. In one embodiment, a strong bias is applied to the substrate in short bursts. Preferably, multiple burst occur during the average transit time for an ion to cross the plasma sheath and reach the substrate surface. Ions are pulsed toward the surface for etching. These ions are not deflected into sidewalls as readily as ions in conventional low energy etch processes due to reduced charge buildup and the relatively low duty cycle of power used to pulse ions toward the substrate surface.

摘要翻译： 用于改进蚀刻工艺的装置和方法。 电源在高功率和低功率周期之间交替产生和维持等离子体放电。 优选地，高功率循环将足够的功率耦合到等离子体中以产生用于蚀刻的高密度离子（>〜1011cm-3）。 优选地，低功率周期允许电子冷却以降低等离子体中的平均随机（热）电子速度。 优选地，低功率循环的持续时间受到限制，以防止对壁的过度等离子体损失或由于负离子和正离子的复合。 本发明的这些和其它方面的优点是平均电子热速度降低，因此较少的电子克服了等离子体鞘并积聚在衬底或掩模层表面上。 单独的电源在高功率和低功率循环之间交替，以将离子加速朝向被蚀刻的衬底。 在一个实施例中，以短脉冲串将强偏压施加到衬底。 优选地，在平均通过时间期间发生多次爆发，以使离子穿过等离子体护套并到达衬底表面。 离子脉冲朝表面进行蚀刻。 这些离子由于电荷累积减少和脉冲离子朝向衬底表面的相对低的功率占空比而不会像传统的低能量蚀刻工艺中的离子一样容易地偏转到侧壁中。

公开(公告)号：US06198074B1

公开(公告)日：2001-03-06

申请号：US08923661

申请日：1997-09-04

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： H01L21205

CPC分类号： C23C16/463 ,  C23C16/46 ,  H01L21/67103 ,  Y10S414/135

摘要： A system and method for thermally processing a substrate. A substrate is heated to a processing temperature at which the substrate is susceptible to plastic deformation or slip. An insulating cover may be removed to initially cool the substrate below such temperature before removal from the system. Gas pressure may also be adjusted to enhance heat transfer during processing and decrease heat transfer prior to removal of the substrate. Susceptors or surfaces for cooling the substrate may also be included in the system. The substrate may be transferred from a heating surface to a cooling surface by moving or rotating the substrate through warm transitional regions to avoid slip.

摘要翻译： 一种用于热处理衬底的系统和方法。 将基板加热到基板容易发生塑性变形或滑动的加工温度。 可以去除绝缘盖以在从系统移除之前首先将衬底冷却至低于该温度。 也可以调节气体压力以增强加工期间的热传递，并且在去除基底之前减少热传递。 用于冷却衬底的吸收体或表面也可以包括在系统中。 衬底可以通过移动或旋转衬底通过温暖的过渡区域从加热表面转移到冷却表面，以避免滑动。

公开(公告)号：US5983828A

公开(公告)日：1999-11-16

申请号：US727209

申请日：1996-10-08

申请人： Stephen E. Savas

发明人： Stephen E. Savas

IPC分类号： H01J37/32 ,  C23C16/00

CPC分类号： H01J37/321 ,  H01J37/32082 ,  H01J37/32706 ,  H01J2237/004 ,  H01J2237/3345

摘要： Apparatus and method for an improved etch process. A power source alternates between high and low power cycles to produce and sustain a plasma discharge. Preferably, the high power cycles couple sufficient power into the plasma to produce a high density of ions (>10.sup.11 cm.sup.-3) for etching. Preferably, the low power cycles allow electrons to cool off to reduce the average random (thermal) electron velocity in the plasma. Preferably, the low power cycle is limited in duration as necessary to prevent excessive plasma loss to the walls or due to recombination of negative and positive ions. It is an advantage of these and other aspects of the present invention that average electron thermal velocity is reduced, so fewer electrons overcome the plasma sheath and accumulate on substrate or mask layer surfaces. A separate power source alternates between high and low power cycles to accelerate ions toward the substrate being etched. In one embodiment, a strong bias is applied to the substrate in short bursts. Preferably, multiple burst occur during the average transit time for an ion to cross the plasma sheath and reach the substrate surface. Ions are pulsed toward the surface for etching. These ions are not deflected into sidewalls as readily as ions in conventional low energy etch processes due to reduced charge buildup and the relatively low duty cycle of power used to pulse ions toward the substrate surface.

摘要翻译： 用于改进蚀刻工艺的装置和方法。 电源在高功率和低功率周期之间交替产生和维持等离子体放电。 优选地，高功率循环将足够的功率耦合到等离子体中以产生用于蚀刻的高密度离子（+ E，ut1 + EE1011cm-3）。 优选地，低功率周期允许电子冷却以降低等离子体中的平均随机（热）电子速度。 优选地，低功率循环的持续时间受到限制，以防止对壁的过度等离子体损失或由于负离子和正离子的复合。 本发明的这些和其它方面的优点是平均电子热速度降低，因此较少的电子克服了等离子体鞘并积聚在衬底或掩模层表面上。 单独的电源在高功率和低功率循环之间交替，以将离子加速朝向被蚀刻的衬底。 在一个实施例中，以短脉冲串将强偏压施加到衬底。 优选地，在平均通过时间期间发生多次爆发，以使离子穿过等离子体护套并到达衬底表面。 离子脉冲朝表面进行蚀刻。 这些离子由于电荷累积减少和脉冲离子朝向衬底表面的相对低的功率占空比而不会像传统的低能量蚀刻工艺中的离子一样容易地偏转到侧壁中。

公开(公告)号：US5811022A

公开(公告)日：1998-09-22

申请号：US340696

申请日：1994-11-15

申请人： Stephen E. Savas ,  Brad S. Mattson

发明人： Stephen E. Savas ,  Brad S. Mattson

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23F4/00 ,  H01J37/32 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/00

CPC分类号： H01J37/32871 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32706 ,  Y10S156/912

摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.