公开(公告)号：US07380107B2

公开(公告)日：2008-05-27

申请号：US10756640

申请日：2004-01-13

申请人： Simon C. Steely, Jr. ,  Gregory Edward Tierney ,  Stephen R. Van Doren

发明人： Simon C. Steely, Jr. ,  Gregory Edward Tierney ,  Stephen R. Van Doren

IPC分类号： G06F15/00

CPC分类号： G06F9/383

摘要： Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.

摘要翻译： 公开了多处理器系统和方法，其采用推测源请求以响应于高速缓存未命中来获得推测数据填充。 在一个实施例中，源处理器响应于高速缓存未命中而产生推测源请求和系统源请求。 响应于推测源请求，至少一个处理器向源处理器提供推测数据填充。 处理器系统响应于系统源请求向处理器提供相干数据填充。

公开(公告)号：US07149852B2

公开(公告)日：2006-12-12

申请号：US10761034

申请日：2004-01-20

申请人： Stephen R. Van Doren ,  Gregory Edward Tierney ,  Simon C. Steely, Jr.

发明人： Stephen R. Van Doren ,  Gregory Edward Tierney ,  Simon C. Steely, Jr.

IPC分类号： G06F12/00

CPC分类号： G06F12/0833 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1044

摘要： Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.

摘要翻译： 公开了用于阻止数据响应的系统和方法。 一个系统包括目标节点，其响应于所请求数据的源广播请求提供包括所请求数据的副本的响应。 目标节点还向与请求的数据相关联的家庭节点提供阻塞消息。 如果阻塞消息与归属节点处的源广播请求匹配，则阻塞消息正在起作用，导致归属节点向源广播请求提供非数据响应。

公开(公告)号：US06636948B2

公开(公告)日：2003-10-21

申请号：US09834551

申请日：2001-04-13

申请人： Simon C. Steely, Jr. ,  Stephen R. Van Doren ,  Madhu Sharna

发明人： Simon C. Steely, Jr. ,  Stephen R. Van Doren ,  Madhu Sharna

IPC分类号： G06F1200

CPC分类号： G06F12/0817

摘要： A performance enhancing change-to-dirty operation (CTD) is disclosed wherein contention among several processors trying to gain ownership of a block of data is obviated by arranging the CTD to always succeed. A method and a system are disclosed where a processor in a multiprocessor system having a copy of data gains assured ownership of data that the processor may then write. The method provides for the possibilities of conditions that may exist and provides a scenario that the requesting processor may have to wait for the ownership. Conditions are handled where the memory is the “owner” of the data and where other processor are requesting ownership, and where copies of the data exist at other processors. The method provides for messages to other processor having copies of the data informing them that the data is now invalid.

摘要翻译： 公开了一种性能提升的改变到脏操作（CTD），其中通过使CTD总是成功地排除尝试获得数据块所有权的若干处理器中的争用。 公开了一种方法和系统，其中具有数据副本的多处理器系统中的处理器确保处理器然后可以写入的数据的所有权。 该方法提供可能存在的条件的可能性并提供请求处理器可能必须等待所有权的情况。 在内存是数据的“所有者”以及其他处理器请求所有权的情况下以及数据的副本存在于其他处理器的情况下处理条件。 该方法向具有数据副本的其他处理器提供消息，通知他们数据现在无效。

公开(公告)号：US20170192921A1

公开(公告)日：2017-07-06

申请号：US14987676

申请日：2016-01-04

申请人： Ren Wang ,  Yipeng Wang ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

发明人： Ren Wang ,  Yipeng Wang ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC分类号： G06F13/37 ,  G06F13/16 ,  G06F12/08

CPC分类号： G06F13/37 ,  G06F9/3004 ,  G06F9/46 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/0868 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/283 ,  G06F2212/6046

摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20100332762A1

公开(公告)日：2010-12-30

申请号：US12495722

申请日：2009-06-30

申请人： Adrian C. Moga ,  Malcolm H. Mandviwalla ,  Stephen R. Van Doren

发明人： Adrian C. Moga ,  Malcolm H. Mandviwalla ,  Stephen R. Van Doren

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/082

摘要： Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy of the data corresponding to the address. Other embodiments are also disclosed.

摘要翻译： 描述了基于窥探响应信息的与目录高速缓存分配有关的方法和装置。 在一个实施例中，响应于确定另一高速缓存代理具有与该地址对应的数据的副本，可以为地址分配目录高速缓存中的条目。 还公开了其他实施例。

公开(公告)号：US07203775B2

公开(公告)日：2007-04-10

申请号：US10337833

申请日：2003-01-07

申请人： Stephen R. Van Doren ,  Gregory E. Tierney

发明人： Stephen R. Van Doren ,  Gregory E. Tierney

IPC分类号： G06F3/00

CPC分类号： G06F9/524

摘要： A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.

摘要翻译： 系统和方法通过在主存储器中提供虚拟缓冲区来避免计算机系统中的死循环，例如循环路由死锁。 计算机系统具有将具有访问主存储器的多个处理器耦合的互连网络。 互连网络包括一个或多个路由代理，每个路由代理具有至少一个用于存储要转发的分组的缓冲器。 当路由代理的缓冲区变满时，路由代理将至少一个数据包传输到虚拟缓冲区中。 通过将数据包从缓冲区传送出去，路由代理释放了允许它接受新数据包的空间。 如果新接受的分组也导致缓冲区变满，则另一分组被传送到虚拟缓冲器中。 重复该过程，直到死锁状态得到解决。 然后从虚拟缓冲区中检索数据包。

公开(公告)号：US07000080B2

公开(公告)日：2006-02-14

申请号：US10263836

申请日：2002-10-03

申请人： Stephen R. Van Doren ,  Gregory E. Tierney

发明人： Stephen R. Van Doren ,  Gregory E. Tierney

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F12/0813 ,  G06F12/082

摘要： A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0 channel for carrying requests for data, a Q1 channel for carrying probes in response to Q0 requests, and a Q2 channel for carrying responses to Q0 requests, a new channel, the QWB channel, which has a higher priority than Q1 but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.

摘要翻译： 基于频道的机制解决计算机系统中的第一处理器将修改后的数据写回存储器和尝试获得修改的数据的副本的第二处理器之间的竞争条件。 除了用于携带对数据的请求的Q 0信道之外，还具有用于响应于Q 0请求携带探针的Q 1信道和用于对Q 0请求进行响应的Q 2信道，具有 优先于Q 1但低于Q 2的优先级也被定义。 当来自第二处理器的转发的Read命令导致第一处理器的高速缓存中的未命中时，由于所请求的存储器块被写回存储器，所以QWB虚拟通道上的第一处理器向存储器发出一个循环命令。 响应于循环命令，存储器将存储器块的写回版本发送到第二处理器。

公开(公告)号：US20150186275A1

公开(公告)日：2015-07-02

申请号：US14142045

申请日：2013-12-27

申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0888

摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。

公开(公告)号：US06892290B2

公开(公告)日：2005-05-10

申请号：US10263738

申请日：2002-10-03

申请人： Stephen R. Van Doren

发明人： Stephen R. Van Doren

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0828

摘要： Early race conditions caused by multiple computer system entities issuing memory reference operations for a given memory block are resolved by creating linked lists identifying the entities. The lists are preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The MAF entries cooperate to form one or more read chains each of which links the entities requesting read access to a particular version of the given memory block. The MAF entries also cooperate to form a single write chain that links the entities requesting write access to the given memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in satisfying its obligations as part of the read and write chains, thereby ensuring that each entity receives the version of the given memory block that it desires.

摘要翻译： 通过为给定的内存块发出内存引用操作的多个计算机系统实体引起的早期竞争条件通过创建标识实体的链表来解决。 优选地通过将信息和状态存储在由实体维护的遗漏地址文件（MAF）条目中来形成。 MAF条目协作形成一个或多个读链，每个读链将请求读访问的实体链接到给定存储块的特定版本。 MAF条目还协作形成一个链接请求写访问的实体到给定的存储块的单个写链。 当期望的存储器块变得可用时，存储在MAF条目中的信息和状态随后被每个实体用来满足其义务作为读取和写入链的一部分，从而确保每个实体接收给定存储器块的版本， 它的愿望

公开(公告)号：US5737546A

公开(公告)日：1998-04-07

申请号：US775552

申请日：1996-12-31

申请人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  Dale R. Keck

发明人： David M. Fenwick ,  Denis J. Foley ,  Stephen R. Van Doren ,  Dale R. Keck

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/368

CPC分类号： G06F13/4213

摘要： Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.

摘要翻译： 耦合到计算机系统中的系统总线的节点的总线接口，系统总线包括地址总线和单独的数据总线。 系统总线操作包括地址和命令事务和数据事务。 在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。 总线接口可以包括用于向地址总线地址和命令事务提供的指挥官地址总线接口装置中的任一个，用于通过地址总线确认接收地址和命令事务的响应方地址总线接口装置，用于 由于在地址总线上发生地址和命令事务而导致数据事务的数据总线的提交;以及响应者数据总线接口装置，用于在数据事务期间在数据总线上传送数据。 在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。 特别地，数据事务的定时和数据事务在数据总线上发生的速率与地址和命令事务的定时以及地址总线上发生地址子事务的速率无关。