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58 条记录 (耗时 0.033 秒)

    Noise suppression for open bit line DRAM architectures
    21.
    发明授权
    Noise suppression for open bit line DRAM architectures 有权
    开放位线DRAM架构的噪声抑制

    公开(公告)号：US06721222B2

    公开(公告)日：2004-04-13

    申请号：US10300398

    申请日：2002-11-19

    申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： G11C702

    CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C11/4094

    摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.

    摘要翻译： 开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。 在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。 屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。 还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。 以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。 在一种方法中，提供虚拟单元和参考单元用于执行信号注入。 本发明的原理特别适用于嵌入式DRAM结构，其中各个单元内的低电荷存储容量降低了可实现的信号电压电平。

    Multiple word-line accessing and accessor
    22.
    发明授权
    Multiple word-line accessing and accessor 有权
    多个字线访问和访问器

    公开(公告)号：US06567329B2

    公开(公告)日：2003-05-20

    申请号：US09941053

    申请日：2001-08-28

    申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： G11C702

    CPC分类号： G11C11/408 ,  G11C11/4097

    摘要： The word-lines and/or bit-lines in a memory are physically arranged to reduce capacitive coupling between signal lines and reference lines. In one embodiment the two bit lines connected to a single sense amplifier are physically separated from each other by bit lines connected to other sense amplifiers. In another embodiment the word-lines are separated from each other by placing them in different metallization layers. In a particular embodiment a single word-line has different portions disposed in different metallization layers.

    摘要翻译： 物理地布置存储器中的字线和/或位线以减少信号线和参考线之间的电容耦合。 在一个实施例中，连接到单个读出放大器的两个位线通过连接到其它读出放大器的位线彼此物理分离。 在另一个实施例中，字线通过将它们放置在不同的金属化层中而彼此分离。 在特定实施例中，单个字线具有设置在不同金属化层中的不同部分。

    ERROR DETECTION AND CORRECTION APPARATUS AND METHOD
    25.
    发明申请
    ERROR DETECTION AND CORRECTION APPARATUS AND METHOD 有权
    错误检测和校正装置和方法

    公开(公告)号：US20140181618A1

    公开(公告)日：2014-06-26

    申请号：US13727561

    申请日：2012-12-26

    申请人： Wei Wu ,  Shih-Lien L. Lu ,  Rajat Agarwal ,  Henry Stracovsky

    发明人： Wei Wu ,  Shih-Lien L. Lu ,  Rajat Agarwal ,  Henry Stracovsky

    IPC分类号： H03M13/15

    CPC分类号： H03M13/151 ,  H03M13/036 ,  H03M13/11 ,  H03M13/152 ,  H03M13/373 ,  H03M13/616

    摘要： Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

    摘要翻译： 描述用于错误检测和校正的装置和方法的实施例。 码字可以具有数据部分和相关联的校验位。 在实施例中，一个或多个错误检测模块可以被配置为检测码字中的多个错误类型。 与一个或多个错误检测模块耦合的一个或多个错误校正模块还可以被配置为一旦一个或多个错误检测模块检测到，则校正多个错误类型的错误。 可以描述和/或要求保护其他实施例。

    METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC)
    26.
    发明申请
    METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) 审中-公开
    使用错误校正码（ECC）编码的缓存标签的直接匹配的方法和设备

    公开(公告)号：US20110161783A1

    公开(公告)日：2011-06-30

    申请号：US12647932

    申请日：2009-12-28

    申请人： Dinesh Somasekhar ,  Jeffrey L. Miller ,  Gunjan H. Pandya ,  Tsung-Yung Chang ,  Wei Wu ,  Shih-Lien L. Lu

    发明人： Dinesh Somasekhar ,  Jeffrey L. Miller ,  Gunjan H. Pandya ,  Tsung-Yung Chang ,  Wei Wu ,  Shih-Lien L. Lu

    IPC分类号： G06F11/10 ,  G06F12/06

    CPC分类号： G06F11/1064 ,  G06F12/0895

    摘要： An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined.

    摘要翻译： 这里描述了直接匹配编码标签的装置和方法。 输入标签地址用纠错码（ECC）编码，以获得编码的传入标签。 编码的输入标签直接与存储的编码标签进行比较; 在一个示例中，该比较结果在编码的输入标签和存储的编码标签之间产生m位差。 在一个所描述的实施例中，ECC能够校正k位并检测k + 1位。 结果，如果m位差在2k + 2位之内，则检测有效的代码编码标签。 例如，如果m位差小于诸如k位的命中阈值，则确定命中，而如果m位差大于诸如k + 1位的未命中阈值， 那么一个小姐是决定的。

    Asymmetric memory cell
    29.
    发明授权
    Asymmetric memory cell 有权
    不对称记忆单元

    公开(公告)号：US07501316B2

    公开(公告)日：2009-03-10

    申请号：US11268098

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： H01L21/82

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

    摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

    摘要翻译： 一些实施例提供了包括体区，源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。