公开(公告)号：US20050248035A1

公开(公告)日：2005-11-10

申请号：US11092524

申请日：2005-03-29

申请人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

发明人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Sun-Ghil Lee ,  In-Soo Jung ,  Young-Eun Lee ,  Deok-Hyung Lee

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/52 ,  H01L27/06 ,  H01L29/40

CPC分类号： H01L29/7842 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/0688

摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

摘要翻译： 半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。 该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。 该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

公开(公告)号：US20080014726A1

公开(公告)日：2008-01-17

申请号：US11701694

申请日：2007-02-02

申请人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02686 ,  H01L29/66651

摘要： Methods of fabricating a semiconductor device are provided. A semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A thin layer is formed on the semiconductor substrate. The thin layer is patterned to form a plurality of spaced apart field structures and to expose therebetween portions of the semiconductor substrate having the single crystalline structure. A non-crystalline layer is formed on the exposed portions of the semiconductor substrate having the single crystalline structure. The non-crystalline layer is planarized to expose upper surfaces of the field structures and define non-crystalline active structures from the non-crystalline layer between the field structures. A laser beam is generated that heats the non-crystalline active structures to change them into single crystalline active structures having substantially the same single crystalline structure as the defined region of the semiconductor substrate.

摘要翻译： 提供制造半导体器件的方法。 提供半导体衬底，其在至少其限定区域内包括单晶结构。 在半导体衬底上形成薄层。 图案化薄层以形成多个间隔开的场结构，并在其间具有单晶结构的半导体衬底的部分露出。 在具有单晶结构的半导体衬底的露出部分上形成非晶层。 非晶层被平坦化以暴露场结构的上表面并且从场结构之间的非晶层限定非结晶活性结构。 产生激光束，其加热非结晶活性结构以将其改变成具有与半导体衬底的限定区域基本上相同的单晶结构的单晶有源结构。

公开(公告)号：US07470603B2

公开(公告)日：2008-12-30

申请号：US11701694

申请日：2007-02-02

申请人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

发明人： Yong-Won Cha ,  Sung-Kwan Kang ,  Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02686 ,  H01L29/66651

摘要： Methods of fabricating a semiconductor device are provided. A semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A thin layer is formed on the semiconductor substrate. The thin layer is patterned to form a plurality of spaced apart field structures and to expose therebetween portions of the semiconductor substrate having the single crystalline structure. A non-crystalline layer is formed on the exposed portions of the semiconductor substrate having the single crystalline structure. The non-crystalline layer is planarized to expose upper surfaces of the field structures and define non-crystalline active structures from the non-crystalline layer between the field structures. A laser beam is generated that heats the non-crystalline active structures to change them into single crystalline active structures having substantially the same single crystalline structure as the defined region of the semiconductor substrate.

公开(公告)号：US20080157095A1

公开(公告)日：2008-07-03

申请号：US12045890

申请日：2008-03-11

申请人： Yong-Hoon Son ,  Yu-Gyun Shin

发明人： Yong-Hoon Son ,  Yu-Gyun Shin

IPC分类号： H01L29/04

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/8221 ,  H01L27/0688

摘要： Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

摘要翻译： 提供具有至少一个单晶硅层的半导体器件的制造方法。 根据这些方法，形成包括硅的第一籽晶层。 然后在第一种子层上形成第一非单晶硅层。 用激光照射第一非单晶硅层，以将第一非单晶硅层转变为第一单晶硅层。 还公开了相应的半导体器件。

公开(公告)号：US20050277235A1

公开(公告)日：2005-12-15

申请号：US11121562

申请日：2005-05-04

申请人： Yong-Hoon Son ,  Yu-Gyun Shin

发明人： Yong-Hoon Son ,  Yu-Gyun Shin

IPC分类号： C30B1/00 ,  C30B3/00 ,  C30B5/00 ,  C30B28/02 ,  H01L21/00 ,  H01L21/20 ,  H01L21/30 ,  H01L21/36 ,  H01L21/46 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/8221 ,  H01L27/0688

摘要： Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

摘要翻译： 提供具有至少一个单晶硅层的半导体器件的制造方法。 根据这些方法，形成包括硅的第一籽晶层。 然后在第一种子层上形成第一非单晶硅层。 用激光照射第一非单晶硅层，以将第一非单晶硅层转变为第一单晶硅层。 还公开了相应的半导体器件。

公开(公告)号：US07364955B2

公开(公告)日：2008-04-29

申请号：US11121562

申请日：2005-05-04

申请人： Yong-Hoon Son ,  Yu-Gyun Shin

发明人： Yong-Hoon Son ,  Yu-Gyun Shin

IPC分类号： H01L21/84

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/8221 ,  H01L27/0688

摘要： Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

摘要翻译： 提供具有至少一个单晶硅层的半导体器件的制造方法。 根据这些方法，形成包括硅的第一籽晶层。 然后在第一种子层上形成第一非单晶硅层。 用激光照射第一非单晶硅层，以将第一非单晶硅层转变为第一单晶硅层。 还公开了相应的半导体器件。

公开(公告)号：US08455316B2

公开(公告)日：2013-06-04

申请号：US13325189

申请日：2011-12-14

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

公开(公告)号：US20110211399A1

公开(公告)日：2011-09-01

申请号：US13102187

申请日：2011-05-06

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： G11C7/00 ,  H01L21/336 ,  H01L21/8242

CPC分类号： H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

摘要翻译： 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

公开(公告)号：US20110039381A1

公开(公告)日：2011-02-17

申请号：US12831577

申请日：2010-07-07

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/7841 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/24 ,  H01L29/42356 ,  H01L29/66272 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.

摘要翻译： 半导体器件包括设置在衬底上并限定彼此分离的第一和第二有源区的沟槽隔离区。 提供从第一有源区向上突出的第一半导体柱。 提供从第二有源区向上突出的第二半导体柱。 提供延伸到跨越第一和第二有源区域的第一栅极掩模。 第一栅极掩模围绕第一和第二半导体柱的上侧壁。 提供了形成在第一栅极掩模下方的与第一和第二有源区分离的第一栅极线以及第一和第二半导体柱的侧壁的周围部分。

公开(公告)号：US20090321816A1

公开(公告)日：2009-12-31

申请号：US12459148

申请日：2009-06-26

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jun Seo ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jun Seo ,  Jong-Hyuk Kang

IPC分类号： H01L29/792 ,  H01L27/088

CPC分类号： H01L27/11551 ,  H01L27/11556

摘要： In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.

摘要翻译： 在垂直型非易失性存储器件中，第一和第二单晶半导体柱被布置成在衬底上彼此面对。 第一和第二单晶半导体柱中的每一个具有与第一，第二，第三和第四侧壁的长方体形状。 第一隧道氧化物层，第一电荷存储层和第一阻挡介电层依次层叠在第一单晶半导体柱的第一侧壁的整个表面上。 第二隧道氧化物层，第二电荷存储层和第二阻挡电介质层依次层叠在第二单晶半导体柱的第一侧壁的整个表面上。 字线与第一和第二阻挡电介质层的表面接触。 字线用于第一和第二单晶半导体柱。