Method of forming semiconductor device including deep vias

    公开(公告)号:US11854966B2

    公开(公告)日:2023-12-26

    申请号:US18156711

    申请日:2023-01-19

    IPC分类号: H01L23/522 G06F30/394

    CPC分类号: H01L23/5226 G06F30/394

    摘要: A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.

    Integrated circuit and method of manufacturing same

    公开(公告)号:US11694013B2

    公开(公告)日:2023-07-04

    申请号:US17860985

    申请日:2022-07-08

    摘要: An integrated circuit includes a first and a set of conductive traces, and a first conductive feature. The second set of conductive traces includes a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor, and a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor. The first conductive feature corresponds to at least a first contact of a first dummy transistor. The first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature. The first n-type transistor being part of a first transmission gate. The first p-type transistor being part of a second transmission gate.

    Integrated circuit having angled conductive feature

    公开(公告)号:US11631661B2

    公开(公告)日:2023-04-18

    申请号:US17317216

    申请日:2021-05-11

    摘要: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.