公开(公告)号：US10937905B2

公开(公告)日：2021-03-02

申请号：US14286202

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  Sameer P. Pendharkar ,  John Lin ,  Guru Mathur ,  Scott Balster ,  Victor Sinow

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

公开(公告)号：US20190157379A1

公开(公告)日：2019-05-23

申请号：US16240194

申请日：2019-01-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108 ,  H01L29/16 ,  H01L27/06 ,  H01L29/66

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

公开(公告)号：US10163678B2

公开(公告)日：2018-12-25

申请号：US14682823

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3205

Abstract: Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.

公开(公告)号：US10103258B2

公开(公告)日：2018-10-16

申请号：US15394636

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L23/52 ,  H01L21/22 ,  H01L21/28 ,  H01L29/423 ,  H01L23/528

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US20180108729A1

公开(公告)日：2018-04-19

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US20180053765A1

公开(公告)日：2018-02-22

申请号：US15681466

申请日：2017-08-21

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US09240446B2

公开(公告)日：2016-01-19

申请号：US14807276

申请日：2015-07-23

Applicant: Texas Instruments Incorporated

Inventor： Guru Mathur ,  Marie Denison ,  Sameer Pendharkar

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

公开(公告)号：US10319809B2

公开(公告)日：2019-06-11

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09876071B2

公开(公告)日：2018-01-23

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US09786665B1

公开(公告)日：2017-10-10

申请号：US15238198

申请日：2016-08-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/76229 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0615 ,  H01L29/0649

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.