公开(公告)号：US20240213333A1

公开(公告)日：2024-06-27

申请号：US18145625

申请日：2022-12-22

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Bill Wofford ,  Jonathan R Garrett ,  Ebenezer Eshun ,  Jungwoo Joh

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/495 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: A microelectronic device includes a III-N semiconductor layer having a top surface with at least one topological structure in the III-N semiconductor layer. The topological structure may be an opening in the III-N semiconductor layer or a protrusion of the III-N semiconductor layer. The microelectronic device also includes a liner including silicon nitride on the topological structure, contacting the III-N semiconductor layer. The microelectronic device further includes a fill material including silicon nitride on the topological structure on the liner. A top surface of the fill material is planar and parallel to the top surface of the III-N semiconductor layer adjacent to the topological structure.

公开(公告)号：US11769824B2

公开(公告)日：2023-09-26

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/0891 ,  H01L29/42316

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20230134698A1

公开(公告)日：2023-05-04

申请号：US17514550

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Sameer Prakash Pendharkar ,  Qhalid RS Fareed ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20

Abstract: A gallium nitride (“GaN”)-based semiconductor device, and method of forming the same. In one example, the semiconductor device includes a channel layer including GaN, and a barrier layer of a first III-N material over the channel layer. The semiconductor device also includes a cap layer of a second III-N material including indium over the barrier layer, wherein the cap layer may have the effect of modifying a threshold voltage and gate leakage current of the semiconductor device.

公开(公告)号：US20230094094A1

公开(公告)日：2023-03-30

申请号：US17491185

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Yoshikazu Kondo

IPC: H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes providing a GaN substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate, the heterojunction supporting a 2-dimensional electron gas (2DEG) channel in the GaN substrate. A composite surface passivation layer is formed over a top surface of the epitaxial layer, wherein the composite surface passivation layer comprises a first passivation layer portion formed proximate to a first region of the GaN device and a second passivation layer portion formed proximate to a second region of the GaN device. The first and second passivation layer portions are disposed laterally adjacent to each other over the epitaxial layer, wherein the first passivation layer portion is formed in a first process and the second passivation layer portion is formed in a second process.

公开(公告)号：US10192799B2

公开(公告)日：2019-01-29

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: G01R31/28 ,  G01R31/12 ,  H01L27/08 ,  H01L29/41 ,  H01L29/20 ,  H01L29/40 ,  H01L29/06 ,  H01L21/66 ,  H01L27/088 ,  H01L29/417 ,  H01L23/544

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20180308773A1

公开(公告)日：2018-10-25

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  G01R31/28 ,  H01L27/088 ,  H01L29/06 ,  H01L23/544 ,  H01L29/20 ,  H01L29/417 ,  G01R31/12 ,  H01L29/40

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2621 ,  G01R31/2642 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US08759879B1

公开(公告)日：2014-06-24

申请号：US13886688

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar ,  Jungwoo Joh

IPC: H01L31/109

CPC classification number: H01L29/2003 ,  H01L29/063 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7786

Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.

Abstract translation: 包含GaN FET的半导体器件在低缺陷层的至少一个III-N半导体层和阻挡层下面的电隔离层中具有n型掺杂。 n型掺杂的片电荷载流子密度为二维电子气的片电荷载流子密度的1〜200％。

公开(公告)号：US20250048667A1

公开(公告)日：2025-02-06

申请号：US18361997

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal Radhakrishna ,  Zhikai Tang ,  Johan Strydom ,  Jungwoo Joh

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872

Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

公开(公告)号：US12113062B2

公开(公告)日：2024-10-08

申请号：US17137784

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H02M3/156 ,  H03K3/037

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L27/0605 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7781 ,  H02M3/156 ,  H03K3/0377

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

公开(公告)号：US20240274705A1

公开(公告)日：2024-08-15

申请号：US18625366

申请日：2024-04-03

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.