公开(公告)号：US11316525B1

公开(公告)日：2022-04-26

申请号：US17158526

申请日：2021-01-26

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Narasimhan Rajagopal ,  Chirag Chandrahas Shetty ,  Prasanth K ,  Neeraj Shrivastava ,  Eeshan Miglani ,  Jagannathan Venkataraman

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/12

Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.

公开(公告)号：US11239854B2

公开(公告)日：2022-02-01

申请号：US17061730

申请日：2020-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Pankaj Gupta ,  Sreenath Narayanan Potty ,  Ajai Paulose ,  Chandrasekhar Sriram ,  Mahesh Ravi Varma ,  Shabbar Abbasi Vejlani ,  Neeraj Shrivastava ,  Himanshu Varshney ,  Divyeshkumar Mahendrabhai Patel ,  Raju Kharataram Chaudhari

IPC: H03M1/36 ,  H03M1/12

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

公开(公告)号：US20210091778A1

公开(公告)日：2021-03-25

申请号：US16575874

申请日：2019-09-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj Shrivastava ,  Sai Aditya Nurani

IPC: H03M1/12 ,  G06F1/26

Abstract: In described examples, a switched capacitor circuit includes an amplifier that generates a first output signal in response to a first sampled input signal. A second sampling circuit is coupled to the amplifier and generates an output signal in response to the first output signal. A first current boost circuit is coupled to the amplifier and the second sampling circuit and provides current to the second sampling circuit when the first output signal is below a first threshold. A second current boost circuit is coupled to the amplifier and the second sampling circuit and receives current from the second sampling circuit when the first output signal is above a second threshold.

公开(公告)号：US10425042B2

公开(公告)日：2019-09-24

申请号：US15859431

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan ,  Shagun Dusad

IPC: H03F3/45 ,  H03F1/30 ,  H03F1/02

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

公开(公告)号：US10084466B1

公开(公告)日：2018-09-25

申请号：US15856185

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

公开(公告)号：US20180191362A1

公开(公告)日：2018-07-05

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09941893B2

公开(公告)日：2018-04-10

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.