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公开(公告)号：US12253356B2
公开(公告)日：2025-03-18
申请号：US17240483
申请日：2021-04-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne , James Norman Hall
Abstract: A calibration circuit providing a programmable voltage generator that is selectively connectable to a first capacitor plate of a capacitive structure to supply a voltage thereto. A reference voltage generator is coupled to the output of the programmable voltage generator and generates a reference voltage. A comparator receives the reference voltage and a discharging voltage from the capacitive structure during a discharge period and, based on those inputs, generates a signal that is output to a digital controller. A constant current source is selectively connectable to the capacitive structure to generate a constant current. Based on the output of the comparator, the constant current, and a count representing a time during which the discharging voltage decreases, the digital controller measures capacitance to calibrate a movable mirror of the capacitive structure. During calibration, the digital controller controls the programmable voltage generator and a second capacitor plate of the capacitive structure.
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公开(公告)号：US11322217B2
公开(公告)日：2022-05-03
申请号：US17003185
申请日：2020-08-26
Applicant: Texas Instruments Incorporated
Inventor： Ashwin Raghunathan , Marco Corsi , Baher Haroun , Seyed Miaad Seyed Aliroteh , Swaminathan Sankaran , Robert Floyd Payne
Abstract: A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.
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公开(公告)号：US10291218B2
公开(公告)日：2019-05-14
申请号：US16023643
申请日：2018-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohammad Elbadry , Robert Floyd Payne , Gerd Schuppener
Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.
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公开(公告)号：US10014899B2
公开(公告)日：2018-07-03
申请号：US15211782
申请日：2016-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne , Lambert Jacob Helleman
CPC classification number: H04B1/40 , G01R31/2884 , G01R31/3004 , G01R31/3016 , G01R31/31711 , H04B17/00 , H04L7/02
Abstract: In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.
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公开(公告)号：US09942066B2
公开(公告)日：2018-04-10
申请号：US15634668
申请日：2017-06-27
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: H04L25/4927 , H03M9/00 , H04L7/0008 , H04L7/0087 , H04L7/042
Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.
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Patent Agency Ranking
公开(公告)号：US20180095494A1
公开(公告)日：2018-04-05
申请号：US15832882
申请日：2017-12-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne
CPC classification number: G06F1/04 , H04B1/04 , H04B1/16 , H04L25/4904
Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.
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27.发明授权公开(公告)号：US09705174B2
公开(公告)日：2017-07-11
申请号：US14555545
申请日：2014-11-26
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne , Gerd Schuppener , Juan Alejandro Herbsommer
CPC classification number: H01P3/16 , H01P11/006
Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.
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公开(公告)号：US09601819B2
公开(公告)日：2017-03-21
申请号：US13854948
申请日：2013-04-01
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Gerd Schuppener , Robert Floyd Payne
CPC classification number: H01P3/16 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01P1/04 , H01P3/121 , H01Q13/00 , H05K1/0239 , H05K1/024 , H05K2201/0187 , H05K2201/0195 , H05K2201/09618 , H05K2201/10098 , Y10T29/49826 , Y10T29/49908
Abstract: A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG.
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29.发明授权Radiating sub-terahertz signal from tapered metallic waveguide into dielectric waveguide 有权从锥形金属波导辐射亚太赫兹信号到介质波导公开(公告)号：US09515367B2
公开(公告)日：2016-12-06
申请号：US14939128
申请日：2015-11-12
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Robert Floyd Payne , Gerd Schuppener , Baher Haroun
IPC: H01P5/00 , H01Q13/00 , H01P3/16 , H01P5/08 , G02B6/44 , H01P11/00 , H01Q1/50 , H01Q19/10 , H04B1/40 , H01Q19/30 , H01P3/12 , H01P5/107 , H01P5/18
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
Abstract translation: 金属波导安装在多层基板上。 金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到 接触多层基板。 锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。
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30.发明授权Dielectric waveguide with non-planar interface surface and mating deformable material 有权具有非平面界面表面和配合可变形材料的介质波导公开(公告)号：US09350063B2
公开(公告)日：2016-05-24
申请号：US13854943
申请日：2013-04-01
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Gerd Schuppener , Robert Floyd Payne
CPC classification number: H01P3/16 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01P1/04 , H01P3/121 , H01Q13/00 , H05K1/0239 , H05K1/024 , H05K2201/0187 , H05K2201/0195 , H05K2201/09618 , H05K2201/10098 , Y10T29/49826 , Y10T29/49908
Abstract: A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end.
Abstract translation: 电介质波导（DWG）具有具有第一介电常数值的介质芯构件。 围绕介电芯构件的包层具有低于第一介电常数的第二介电常数值。 DWG的配合端构造成非平面形状，用于与具有匹配的非平面形配合端的第二DWG配合。
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