公开(公告)号：US20240362023A1

公开(公告)日：2024-10-31

申请号：US18227707

申请日：2023-07-28

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Vinod Kumar Paparaju

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3802

Abstract: An example apparatus includes example packet decode circuitry to decode an instruction packet for programmable circuitry into at least one instruction. Additionally, the example apparatus includes example instruction mapping circuitry to disregard a pad instruction included in the at least one instruction, the pad instruction having not been assigned to any functional unit of the programmable circuitry.

公开(公告)号：US20230068811A1

公开(公告)日：2023-03-02

申请号：US18047511

申请日：2022-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US20220350699A1

公开(公告)日：2022-11-03

申请号：US17866659

申请日：2022-07-18

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi ,  David Peter Foley

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/16 ,  G06F11/30

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

公开(公告)号：US11061783B2

公开(公告)日：2021-07-13

申请号：US16396941

申请日：2019-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Srinivasa Chakravarthy Bs

IPC: G06F11/16 ,  G06F11/10

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

公开(公告)号：US10177747B2

公开(公告)日：2019-01-08

申请号：US15274576

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Alexander Tessarolo ,  Saya Goud Langadi

IPC: G01R23/02 ,  H03K3/03 ,  H03K5/159 ,  H03K19/20

Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.

公开(公告)号：US10062451B2

公开(公告)日：2018-08-28

申请号：US15346737

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Saya Goud Langadi

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/44 ,  H03M13/09 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/12 ,  G11C29/18 ,  G11C29/40

CPC classification number: G11C29/42 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1068 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/44 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/4002 ,  H03M13/09 ,  H03M13/093

Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

公开(公告)号：US20170149418A1

公开(公告)日：2017-05-25

申请号：US15274576

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Alexander Tessarolo ,  Saya Goud Langadi

IPC: H03K3/03 ,  H03K5/159 ,  H03K19/20

CPC classification number: H03K3/0315 ,  G01R23/02 ,  H03K5/159 ,  H03K19/20

Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.

公开(公告)号：US20170133106A1

公开(公告)日：2017-05-11

申请号：US15346737

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Saya Goud Langadi

IPC: G11C29/42 ,  G11C29/44 ,  H03M13/09 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/106 ,  G06F11/1068 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C29/44 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/4002 ,  H03M13/09 ,  H03M13/093

Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.