公开(公告)号：US20230229607A1

公开(公告)日：2023-07-20

申请号：US18126602

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

CPC classification number: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US20230179215A1

公开(公告)日：2023-06-08

申请号：US17541781

申请日：2021-12-03

Applicant: Texas Instruments Incorporated

Inventor： Jayawardan Janardhanan ,  Yogesh Darwhekar ,  Subhashish Mukherjee

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

公开(公告)号：US11290118B2

公开(公告)日：2022-03-29

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Theertham ,  Jagdish Chand ,  Yogesh Darwhekar ,  Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Uday Kiran Meda ,  Arpan Sureshbhai Thakkar ,  Apoorva Bhatia ,  Pranav Kumar

IPC: H03L7/23 ,  H03M1/66 ,  H03L7/085 ,  H03L7/099

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

公开(公告)号：US11082271B2

公开(公告)日：2021-08-03

申请号：US16900010

申请日：2020-06-12

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Abhijit Anant Patki ,  Madhulatha Bonu ,  Kumar Anurag Shrivastava

IPC: H04L27/22 ,  H03D3/00 ,  H03L7/081 ,  H04L27/227 ,  H03K19/21 ,  H03L7/087 ,  H03L7/113 ,  H04L7/033 ,  H04L7/00

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

公开(公告)号：US10978996B2

公开(公告)日：2021-04-13

申请号：US16670741

申请日：2019-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Madhulatha Bonu

IPC: H03B5/06 ,  H03B5/04 ,  H03B5/12 ,  H03L7/00 ,  H03L3/00

Abstract: Methods and apparatus generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.

公开(公告)号：US20200266131A1

公开(公告)日：2020-08-20

申请号：US16867352

申请日：2020-05-05

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Michael Sutton ,  Sreenivasan K. Koduri ,  Subhashish Mukherjee

IPC: H01L23/495

Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

公开(公告)号：US20200067453A1

公开(公告)日：2020-02-27

申请号：US16670741

申请日：2019-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Madhulatha Bonu

IPC: H03B5/06 ,  H03B5/12 ,  H03L3/00 ,  H03L7/00 ,  H03B5/04

Abstract: Methods and apparatus generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.

公开(公告)号：US10547352B2

公开(公告)日：2020-01-28

申请号：US15454797

申请日：2017-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Venugopal Gopinathan

IPC: H04B5/00 ,  H01L23/66 ,  H03B5/08 ,  H01L23/64

Abstract: In described examples, a first die includes a primary LC tank oscillator having a natural frequency of oscillation to induce a forced oscillation in a secondary LC tank oscillator of a separate second die via a magnetic coupling between the primary LC tank oscillator and the secondary LC tank oscillator.

公开(公告)号：US10546780B2

公开(公告)日：2020-01-28

申请号：US15343557

申请日：2016-11-04

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US10236826B1

公开(公告)日：2019-03-19

申请号：US16000972

申请日：2018-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Darwhekar ,  Apoorva Bhatia ,  Subhashish Mukherjee

IPC: H04B1/26 ,  H03B5/18 ,  H04B1/16 ,  H04B1/04 ,  H03D7/14

Abstract: A down converter, including first and second biasing circuits, mixer, and transformer coupled to receive amplifier output signal. The first and second biasing circuits each include a biasing transistor and a first and second node, respectively. Mixer includes first and second transistors coupled to first node and third and fourth transistors coupled to second node. The second and fourth transistors are coupled to a third node. The first and third transistors are coupled to a fourth node. Mixer also includes a first resistor coupled to the fourth node and a supply voltage node and a second resistor coupled to the third node and a supply voltage node. Transformer includes a primary winding coupled to receive the amplifier output signal and to a supply voltage and a secondary winding coupled to mixer and first biasing circuit at first node and coupled to mixer and second biasing circuit at second node.