公开(公告)号：US20200303418A1

公开(公告)日：2020-09-24

申请号：US16563627

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka SAKUMA ,  Hidenori Miyagawa ,  Shosuke Fujii ,  Kiwamu Sakuma ,  Fumitaka Arai

IPC: H01L27/11597 ,  H01L23/528 ,  H01L29/51 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

公开(公告)号：US10236254B1

公开(公告)日：2019-03-19

申请号：US15923488

申请日：2018-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka Arai ,  Satoshi Nagashima

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device includes first and second insulating plates, a stacked body provided between the first insulating plate and the second insulating plate, and a semiconductor member. The stacked body includes interconnect layers. The interconnect layer includes a first interconnect portion contacting the first insulating plate, a second interconnect portion contacting the second insulating plate, a third interconnect portion, a fourth interconnect portion, fifth and sixth interconnect portions are separated from the first and the second insulating plates. The fifth interconnect portion is connected to the first interconnect portion via the third interconnect portion, and is insulated from the second interconnect portion. The sixth interconnect portion is connected to the second interconnect portion via the fourth interconnect portion, and is insulated from the first interconnect portion. The semiconductor member is disposed between the fifth interconnect portion and the sixth interconnect portion.

公开(公告)号：US10229924B2

公开(公告)日：2019-03-12

申请号：US15686292

申请日：2017-08-25

Applicant: Toshiba Memory Corporation

Inventor： Wataru Sakamoto ,  Tatsuya Kato ,  Yuta Watanabe ,  Katsuyuki Sekine ,  Toshiyuki Iwamoto ,  Fumitaka Arai

IPC: H01L23/52 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.

公开(公告)号：US20190006419A1

公开(公告)日：2019-01-03

申请号：US16102958

申请日：2018-08-14

Applicant: Toshiba Memory Corporation

Inventor： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11568 ,  H01L27/115 ,  H01L27/105 ,  H01L21/762 ,  H01L21/3213

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US10134750B2

公开(公告)日：2018-11-20

申请号：US14838854

申请日：2015-08-28

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya Kato ,  Wataru Sakamoto ,  Fumitaka Arai

IPC: H01L29/788 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11548

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

公开(公告)号：US10103155B2

公开(公告)日：2018-10-16

申请号：US15449481

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kohei Sakaike ,  Toshiyuki Iwamoto ,  Tatsuya Kato ,  Keisuke Kikutani ,  Fumitaka Arai ,  Satoshi Nagashima ,  Koichi Sakata ,  Yuta Watanabe

IPC: H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.

公开(公告)号：US09966381B2

公开(公告)日：2018-05-08

申请号：US15267776

申请日：2016-09-16

Applicant: Toshiba Memory Corporation

Inventor： Fumitaka Arai ,  Tatsuya Kato ,  Satoshi Nagashima ,  Katsuyuki Sekine ,  Yuta Watanabe ,  Keisuke Kikutani ,  Atsushi Murakoshi

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L29/788 ,  H01L21/3105 ,  H01L27/11556 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/31051 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.

公开(公告)号：US09847342B2

公开(公告)日：2017-12-19

申请号：US15268126

申请日：2016-09-16

Applicant: Toshiba Memory Corporation

Inventor： Satoshi Nagashima ,  Katsumi Yamamoto ,  Kohei Sakaike ,  Tatsuya Kato ,  Keisuke Kikutani ,  Fumitaka Arai ,  Atsushi Murakoshi ,  Shunichi Takeuchi ,  Katsuyuki Sekine

IPC: H01L29/788 ,  H01L27/11556 ,  H01L29/51 ,  H01L27/11521 ,  H01L29/06 ,  H01L21/31 ,  H01L21/306

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L29/0649

Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.

公开(公告)号：US11227832B2

公开(公告)日：2022-01-18

申请号：US16564584

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji Hosotani ,  Fumitaka Arai ,  Keisuke Nakatsuka ,  Nobuyuki Momo ,  Motohiko Fujimatsu

IPC: H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.

公开(公告)号：US11101325B2

公开(公告)日：2021-08-24

申请号：US16102958

申请日：2018-08-14

Applicant: Toshiba Memory Corporation

Inventor： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC: H01L27/24 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L45/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/51

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.