公开(公告)号：US10763122B2

公开(公告)日：2020-09-01

申请号：US15695918

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Soichi Yamazaki ,  Kazuhito Furumoto ,  Kosuke Horibe ,  Keisuke Kikutani ,  Atsuko Sakata ,  Junichi Wada ,  Toshiyuki Sasaki

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/1157

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.

公开(公告)号：US20180097011A1

公开(公告)日：2018-04-05

申请号：US15819003

申请日：2017-11-21

Applicant: Toshiba Memory Corporation

Inventor： Koichi Sakata ,  Yuta Watanabe ,  Keisuke Kikutani ,  Satoshi Nagashima ,  Fumitaka Arai ,  Toshiyuki Iwamoto

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L21/311

Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.

公开(公告)号：US09853050B2

公开(公告)日：2017-12-26

申请号：US15242763

申请日：2016-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke Kikutani

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, at least one stacked body, and a first insulating film. The stacked body includes a first end portion positioned at an end in at least one of a first direction and a second direction that crosses the first direction along a surface of the substrate, the plurality of electrode layers being formed into stairs in the first end portion, each of the plurality of electrode layers having a step in the first end portion. The first insulating film is provided on the substrate and includes first and second surfaces, the first and second surfaces surrounding the first end portion, the first surface being crossing a direction that the steps are formed, the second surface being positioned along the direction that the steps are formed.

公开(公告)号：US10930665B2

公开(公告)日：2021-02-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US10903238B2

公开(公告)日：2021-01-26

申请号：US16750237

申请日：2020-01-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Katsumi Yamamoto ,  Keisuke Kikutani

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.

公开(公告)号：US10103155B2

公开(公告)日：2018-10-16

申请号：US15449481

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kohei Sakaike ,  Toshiyuki Iwamoto ,  Tatsuya Kato ,  Keisuke Kikutani ,  Fumitaka Arai ,  Satoshi Nagashima ,  Koichi Sakata ,  Yuta Watanabe

IPC: H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.

公开(公告)号：US09966381B2

公开(公告)日：2018-05-08

申请号：US15267776

申请日：2016-09-16

Applicant: Toshiba Memory Corporation

Inventor： Fumitaka Arai ,  Tatsuya Kato ,  Satoshi Nagashima ,  Katsuyuki Sekine ,  Yuta Watanabe ,  Keisuke Kikutani ,  Atsushi Murakoshi

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L29/788 ,  H01L21/3105 ,  H01L27/11556 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/31051 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.

公开(公告)号：US09847342B2

公开(公告)日：2017-12-19

申请号：US15268126

申请日：2016-09-16

Applicant: Toshiba Memory Corporation

Inventor： Satoshi Nagashima ,  Katsumi Yamamoto ,  Kohei Sakaike ,  Tatsuya Kato ,  Keisuke Kikutani ,  Fumitaka Arai ,  Atsushi Murakoshi ,  Shunichi Takeuchi ,  Katsuyuki Sekine

IPC: H01L29/788 ,  H01L27/11556 ,  H01L29/51 ,  H01L27/11521 ,  H01L29/06 ,  H01L21/31 ,  H01L21/306

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L29/0649

Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.

公开(公告)号：US20200235117A1

公开(公告)日：2020-07-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke HORIBE ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11565 ,  G11C16/04

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US10573660B2

公开(公告)日：2020-02-25

申请号：US16105892

申请日：2018-08-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Katsumi Yamamoto ,  Keisuke Kikutani

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.