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公开(公告)号:US11227832B2
公开(公告)日:2022-01-18
申请号:US16564584
申请日:2019-09-09
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji Hosotani , Fumitaka Arai , Keisuke Nakatsuka , Nobuyuki Momo , Motohiko Fujimatsu
IPC: H01L23/528 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , G11C16/04
Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
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公开(公告)号:US10049711B2
公开(公告)日:2018-08-14
申请号:US15257085
申请日:2016-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke Nakatsuka , Tadashi Miyakawa , Katsuhiko Hoya , Takeshi Hamamoto , Hiroyuki Takenaka
Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.
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公开(公告)号:US10991713B2
公开(公告)日:2021-04-27
申请号:US16298865
申请日:2019-03-11
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Satoshi Nagashima , Keisuke Nakatsuka , Fumitaka Arai , Shinya Arai , Yasuhiro Uchiyama
IPC: H01L27/11578 , G11C11/40 , H01L27/1157
Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
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公开(公告)号:US10978471B2
公开(公告)日:2021-04-13
申请号:US16351207
申请日:2019-03-12
Applicant: Toshiba Memory Corporation
Inventor: Keisuke Nakatsuka
IPC: H01L27/11582 , H01L27/1157 , H01L27/11565
Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
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公开(公告)号:US09934834B2
公开(公告)日:2018-04-03
申请号:US15248247
申请日:2016-08-26
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke Nakatsuka , Katsuhiko Hoya
CPC classification number: G11C11/1673 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697
Abstract: A magnetoresistive memory device includes a variable resistance element and a read circuit. The resistance element has a resistance state, which is one of switchable first and second resistance states. The first and second resistance states exhibit different resistances. Each of the first and second resistance states is reached by a current flowing through the variable resistance element in one of opposing first and second directions. The read circuit passes a read current through the variable resistance element autonomously in the first or second direction in accordance with the resistance state of the variable resistance element.
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公开(公告)号:US11107508B2
公开(公告)日:2021-08-31
申请号:US16562372
申请日:2019-09-05
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji Hosotani , Fumitaka Arai , Keisuke Nakatsuka
IPC: H01L27/11578 , G11C5/06 , H01L23/48 , H01L27/1157 , H01L27/11582 , H01L27/11565 , H01L27/11519 , G11C16/30 , H01L27/11556 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26 , H01L27/11524
Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
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公开(公告)号:US10311929B2
公开(公告)日:2019-06-04
申请号:US15835988
申请日:2017-12-08
Applicant: TOSHIBA MEMORY CORPORATION , SK HYNIX INC.
Inventor: Hisanori Aikawa , Tatsuya Kishi , Keisuke Nakatsuka , Satoshi Inaba , Masaru Toko , Keiji Hosotani , Jae Yun Yi , Hong Ju Suh , Se Dong Kim
IPC: G11C11/16 , G11C8/08 , G11C8/12 , G11C13/00 , H01L43/08 , H01L45/00 , H01L27/22 , H01L27/24 , G11C5/06
Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
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公开(公告)号:US10020040B2
公开(公告)日:2018-07-10
申请号:US15455906
申请日:2017-03-10
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke Nakatsuka , Tsuneo Inaba , Yutaka Shirai
CPC classification number: G11C11/1673 , G11C7/04 , G11C7/065 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/1693 , G11C11/5642 , G11C16/26 , G11C16/28
Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.
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公开(公告)号:US10748920B2
公开(公告)日:2020-08-18
申请号:US16126209
申请日:2018-09-10
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke Nakatsuka
IPC: H01L29/76 , H01L27/11582 , H01L29/40 , H01L27/11565 , H01L21/28 , H01L29/792
Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrode films, a semiconductor member, a tunneling insulating film, a charge storage member, and a blocking insulating film. The plurality of electrode films are arranged to be separated from each other along a first direction. The semiconductor member extends in the first direction. The tunneling insulating film is provided between the semiconductor member and the electrode films. The charge storage member is provided between the tunneling insulating film and the electrode films. The blocking insulating film is provided between the charge storage member and the electrode films. The blocking insulating film includes a first film contacting the charge storage film and including carbon-containing silicon oxide, and a second film contacting the electrode films and including hafnium oxide or aluminum oxide.
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公开(公告)号:US11121147B2
公开(公告)日:2021-09-14
申请号:US16559380
申请日:2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke Nakatsuka , Yoshitaka Kubota , Tetsuaki Utsumi , Yoshiro Shimojo , Ryota Katsumata
IPC: H01L27/11519 , H01L27/11573 , H01L27/11578 , H01L27/1157 , H01L27/11551 , H01L27/11524 , H01L27/11529 , H01L27/11565
Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
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