公开(公告)号：US4967339A

公开(公告)日：1990-10-30

申请号：US179554

申请日：1988-04-08

申请人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

发明人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/355

CPC分类号： G06F9/30014 ,  G06F9/342 ,  G06F9/3889

摘要： A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

摘要翻译： 处理器通过操作数有效地址计算单元执行流水线并行处理，用于计算执行指令所需的操作数有效地址和执行指令的指令执行单元。 执行64位宽的数据操作，使得在操作数有效地址单元中的算术装置中执行高阶32位操作，并且在指令执行单元中的另一个运算装置中执行低位32位操作。 进位从低位32位运算器传输到高位32位运算器件。 如此连接的算术装置可以作为运算装置执行数据操作的64位。

公开(公告)号：US3947818A

公开(公告)日：1976-03-30

申请号：US531161

申请日：1974-12-09

申请人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

发明人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

IPC分类号： G06F13/36 ,  G06F13/40 ,  H04L12/40 ,  H04L29/08 ,  H04Q9/00

CPC分类号： G06F13/4036

摘要： A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.

摘要翻译： 用于连接多个总线的信息传输系统中的总线耦合器或总线窗口，其中多个运算单元，多个存储器或存储单元以及多个输入 - 输出单元通过站单独连接。 总线耦合器包括用于防止在总线之间的通信中可能发生的死锁的死锁控制电路。

公开(公告)号：US5968160A

公开(公告)日：1999-10-19

申请号：US923632

申请日：1997-09-04

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

公开(公告)号：US5506982A

公开(公告)日：1996-04-09

申请号：US278245

申请日：1994-07-21

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/06

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

公开(公告)号：US5297239A

公开(公告)日：1994-03-22

申请号：US883592

申请日：1992-05-13

申请人： Kenichi Kurosawa ,  Masaru Shimada ,  Hirokazu Hirayama ,  Tadaaki Bandoh ,  Kiyomi Mori

发明人： Kenichi Kurosawa ,  Masaru Shimada ,  Hirokazu Hirayama ,  Tadaaki Bandoh ,  Kiyomi Mori

IPC分类号： G06F9/44 ,  G06F17/30 ,  G06N5/04 ,  G06F15/18 ,  G06F15/40

CPC分类号： G06N5/046 ,  G06N5/047

摘要： High-speed inference method and system for a production system represented by an expert system. A knowledge base comprised of a rule and a fact possessing a plurality of attributes is converted into machine language instructions executable by a processor to execute inference. The machine language instruction of the fact has the function of transferring a value of the fact to a specified location and the machine language instruction of the rule has the function of performing matching decision by referring to the specified location. The number of pattern matching operations can be decreased and the interpretation overhead can be reduced to ensure high-speed inference.

摘要翻译： 专家系统代表的生产系统的高速推理方法和系统。 由规则和具有多个属性的事实组成的知识库被转换成可由处理器执行以执行推理的机器语言指令。 该事实的机器语言指令具有将事实值转移到指定位置的功能，并且规则的机器语言指令具有参照指定位置执行匹配决定的功能。 可以减少模式匹配操作的数量，并且可以减少解释开销以确保高速推断。

公开(公告)号：US07111187B2

公开(公告)日：2006-09-19

申请号：US10701447

申请日：2003-11-06

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 与原始时钟信号K锁相并且具有预定占空比的至少一个第二时钟信号K 1 1和其操作时序被第二时钟信号K _{1 <1>，并且由至少一对逻辑器件之间提供的接口的操作时序由时钟信号K 1 1同步地控制。}

公开(公告)号：US5542083A

公开(公告)日：1996-07-30

申请号：US460601

申请日：1995-06-02

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。

公开(公告)号：US5287465A

公开(公告)日：1994-02-15

申请号：US549916

申请日：1990-07-09

申请人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

发明人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177 ,  G06F9/00

CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.

摘要翻译： 当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。 当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。 为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。 指令根据处理状态判别标志在算术单元中进行处理。 以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。 此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一 到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。 通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令 并且执行地址nm + h至（n + 1）m的指令。 以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

公开(公告)号：US5274829A

公开(公告)日：1993-12-28

申请号：US114720

申请日：1987-10-28

申请人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

发明人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F15/78 ,  G06F1/00

CPC分类号： G06F9/268 ,  G06F9/26 ,  G06F9/328

摘要： A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it is determined whether the micro instruction is stored in the on-chip ROM or the off-chip memory, and the micro instruction is accessed on the basis of this determination. A cache memory may also be provided on the chip for providing high speed repeat access to micro instructions stored in the off-chip memory.

摘要翻译： 一种数据处理装置，其通过将经常使用的微指令存储在片上ROM中以及在片外存储器中较少使用的微指令，允许以高速读取大量微指令。 根据要访问的微指令的地址，确定微指令是存储在片上ROM还是片外存储器中，并且基于该确定来访问微指令。 还可以在芯片上提供高速缓冲存储器，以提供对存储在片外存储器中的微指令的高速重复访问。

公开(公告)号：US5784630A

公开(公告)日：1998-07-21

申请号：US367928

申请日：1995-01-03

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.