公开(公告)号：US12283521B2

公开(公告)日：2025-04-22

申请号：US18420209

申请日：2024-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US20250107203A1

公开(公告)日：2025-03-27

申请号：US18974363

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8234

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

公开(公告)号：US12166092B2

公开(公告)日：2024-12-10

申请号：US18329126

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8234

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

公开(公告)号：US20240387664A1

公开(公告)日：2024-11-21

申请号：US18788305

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su

IPC: H01L29/417 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

公开(公告)号：US20240363535A1

公开(公告)日：2024-10-31

申请号：US18771066

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L21/76892 ,  H01L29/401 ,  H01L29/41775 ,  H01L21/76885

Abstract: The semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, and a second dielectric feature. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner.

公开(公告)号：US12132092B2

公开(公告)日：2024-10-29

申请号：US17743992

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4238 ,  H01L21/76804 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/4933 ,  H01L29/6656

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US12125852B2

公开(公告)日：2024-10-22

申请号：US18360895

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3086

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US12068382B2

公开(公告)日：2024-08-20

申请号：US17728679

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US12021025B2

公开(公告)日：2024-06-25

申请号：US18195000

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886

Abstract: A semiconductor structure (MG) includes a metal gate structure disposed over a semiconductor substrate, a dielectric layer disposed adjacent to the MG, a source/drain (S/D) feature disposed adjacent to the dielectric layer, and a S/D contact disposed over the S/D feature. The S/D contact includes a first metal layer disposed over the S/D feature and a second metal layer disposed on the first metal layer.

公开(公告)号：US12009265B2

公开(公告)日：2024-06-11

申请号：US18068110

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.