公开(公告)号：US20180366375A1

公开(公告)日：2018-12-20

申请号：US15628345

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Chih-Sheng Chang ,  Cheng-Hsien Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

公开(公告)号：US10056498B2

公开(公告)日：2018-08-21

申请号：US15401463

申请日：2017-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ling-Yen Yeh ,  Chih-Sheng Chang ,  Wilman Tsai ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02527 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/66969 ,  H01L29/778

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

公开(公告)号：US09741829B2

公开(公告)日：2017-08-22

申请号：US14714227

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US11563102B2

公开(公告)日：2023-01-24

申请号：US17026562

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US11145676B1

公开(公告)日：2021-10-12

申请号：US16880998

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Sheng Chang ,  Tzu-Chiang Chen ,  Jin Cai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L43/08 ,  G11C11/16

Abstract: A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.

公开(公告)号：US11056401B2

公开(公告)日：2021-07-06

申请号：US16700227

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Cheng-Hsien Wu ,  Chih-Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

Abstract: A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.

公开(公告)号：US11043489B2

公开(公告)日：2021-06-22

申请号：US16049172

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wen Chang ,  Hong-Nien Lin ,  Chien-Hsing Lee ,  Chih-Sheng Chang ,  Ling-Yen Yeh ,  Wilman Tsai ,  Yee-Chia Yeo

IPC: H01L21/02 ,  H01L27/06 ,  H01L27/1159 ,  H01L29/417 ,  H01L27/088 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L49/02

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

公开(公告)号：US10741678B2

公开(公告)日：2020-08-11

申请号：US15798273

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh ,  Chien-Hsing Lee

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L29/51 ,  H01L29/78

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US10734472B2

公开(公告)日：2020-08-04

申请号：US16392158

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chien-Hsing Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L49/02 ,  H01L27/1159 ,  H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L27/11585 ,  H01L29/51 ,  H01L29/66

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

公开(公告)号：US20190165103A1

公开(公告)日：2019-05-30

申请号：US15904699

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L29/51 ,  H01L21/465 ,  H01L29/08 ,  H01L21/768 ,  H01L29/24 ,  H01L29/78 ,  H01L29/06 ,  H01L21/441

Abstract: A semiconductor device includes a fin structure, a channel layer and a gate stack. The channel layer is disposed on sidewalls of the fin structure, wherein the channel layer contains a two-dimensional (2D) material. The gate stack is disposed over the channel layer, wherein the gate stack includes a ferroelectric layer.