公开(公告)号：US20190333822A1

公开(公告)日：2019-10-31

申请号：US15964177

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US20170316943A1

公开(公告)日：2017-11-02

申请号：US15141951

申请日：2016-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Henry Kwong ,  Chih-Yung Lin ,  Po-Nien Chen ,  Chen Hua Tsai

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/36

CPC classification number: H01L29/41791 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US20240395628A1

公开(公告)日：2024-11-28

申请号：US18788006

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes providing a structure having a first channel member, a second channel member, and a third channel member, forming a first oxide layer, a second oxide layer, and a third oxide layer, the first oxide layer wrapping the first channel member, the second oxide layer wrapping the second channel member, the third oxide layer wrapping the third channel member, forming a first capping layer, a second capping layer, and a third capping layer over the first oxide layer, the second oxide layer, and the third oxide layer, respectively, removing the second capping layer, and after removing the second capping layer performing an oxide growing process to increase a thickness of the second oxide layer.

公开(公告)号：US11791217B2

公开(公告)日：2023-10-17

申请号：US17246998

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823462 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

公开(公告)号：US11037831B2

公开(公告)日：2021-06-15

申请号：US16737447

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10998237B2

公开(公告)日：2021-05-04

申请号：US16853474

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US20210091172A1

公开(公告)日：2021-03-25

申请号：US17114108

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L49/02 ,  H01L27/07 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

公开(公告)号：US20200286993A1

公开(公告)日：2020-09-10

申请号：US16881467

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US10411085B2

公开(公告)日：2019-09-10

申请号：US15593479

申请日：2017-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US10355071B2

公开(公告)日：2019-07-16

申请号：US15593479

申请日：2017-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.