公开(公告)号：US20190139837A1

公开(公告)日：2019-05-09

申请号：US16233243

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.

公开(公告)号：US10177043B1

公开(公告)日：2019-01-08

申请号：US15793163

申请日：2017-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

Abstract: A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.

公开(公告)号：US09620503B1

公开(公告)日：2017-04-11

申请号：US14941662

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-I Liao ,  Shih-Chieh Chang ,  Chun-Ju Huang ,  Chien-Wei Lee ,  Chii-Ming Wu

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET including a substrate, a plurality of isolators, a gate stack, and strained material portions is provided. The substrate includes at least two fins thereon. The isolators are disposed on the substrate, and each of the insulators between the fins has a recess profile. The gate stack is disposed over portions of the fins and over the insulators. The strained material portions cover the fins revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US20170098711A1

公开(公告)日：2017-04-06

申请号：US15071206

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chii-Ming Wu

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L29/7856 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.

公开(公告)号：US09570557B2

公开(公告)日：2017-02-14

申请号：US14700067

申请日：2015-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen Cheng Chou ,  Chung-Ren Sun ,  Chii-Ming Wu ,  Cheng-Ta Wu ,  Tzu kai Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/306

CPC classification number: H01L29/1054 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76237 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.

Abstract translation: 制造鳍状场效应晶体管（FinFET）的技术包括提供具有翅片结构的衬底，并形成具有第一表面轮廓的顶表面的隔离区域。 使用与顶表面的边缘部分倾斜的角度注入掺杂剂种类。 然后使用蚀刻工艺除去边缘部分。 在这方面，基于大于在顶表面的其它部分使用的蚀刻速率的蚀刻速率，将隔离区域修改为具有第二表面轮廓。 第二表面轮廓具有小于对应于第一表面轮廓的台阶高度的台阶高度。 倾斜注入和蚀刻处理可以在栅极结构形成之后，在栅极结构形成之后，但在鳍结构凹陷之前，或鳍结构凹陷之后进行。

公开(公告)号：US11532698B2

公开(公告)日：2022-12-20

申请号：US16567247

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Hai-Dang Trinh ,  Fa-Shen Jiang

IPC: H01L49/02 ,  H01L23/522

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

公开(公告)号：US11450555B2

公开(公告)日：2022-09-20

申请号：US17200198

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.

公开(公告)号：US11152568B2

公开(公告)日：2021-10-19

申请号：US16724673

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Fa-Shen Jiang

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

公开(公告)号：US11131025B2

公开(公告)日：2021-09-28

申请号：US16907714

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Chii-Ming Wu ,  Hai-Dang Trinh

IPC: C23C16/52 ,  H01L21/67 ,  H04N5/232 ,  C23C16/455 ,  C23C14/34 ,  G06T7/00 ,  C23C14/54 ,  C23C14/52 ,  G06T7/80

Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.

公开(公告)号：US10950490B2

公开(公告)日：2021-03-16

申请号：US16222769

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.