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    HIGH-VOLTAGE NANO-SHEET TRANSISTOR
    21.
    发明申请
    HIGH-VOLTAGE NANO-SHEET TRANSISTOR 有权

    公开(公告)号：US20210408234A1

    公开(公告)日：2021-12-30

    申请号：US16916951

    申请日：2020-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Yih Wang

    IPC: H01L29/06 ,  H01L27/088 ,  H01L27/112 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

    Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

    Gate-all-around structure with self substrate isolation and methods of forming the same
    23.
    发明授权
    Gate-all-around structure with self substrate isolation and methods of forming the same 有权

    公开(公告)号：US11145765B2

    公开(公告)日：2021-10-12

    申请号：US16583449

    申请日：2019-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

    Semiconductor devices
    24.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11088256B2

    公开(公告)日：2021-08-10

    申请号：US16667947

    申请日：2019-10-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

    Semiconductor devices
    25.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11088255B2

    公开(公告)日：2021-08-10

    申请号：US16415193

    申请日：2019-05-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

    Method for metal gate cut and structure thereof
    26.
    发明授权
    Method for metal gate cut and structure thereof 有权

    公开(公告)号：US11081356B2

    公开(公告)日：2021-08-03

    申请号：US16366511

    申请日：2019-03-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088

    Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.

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