公开(公告)号：US12046665B2

公开(公告)日：2024-07-23

申请号：US18160256

申请日：2023-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu-Chiang Chen

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/454 ,  H01L29/66795 ,  H01L29/785

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US20230397442A1

公开(公告)日：2023-12-07

申请号：US18447805

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/42392 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

公开(公告)号：US11563102B2

公开(公告)日：2023-01-24

申请号：US17026562

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US20220416085A1

公开(公告)日：2022-12-29

申请号：US17884285

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L29/24 ,  H01L27/11597 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H01L27/1159

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US20220231153A1

公开(公告)日：2022-07-21

申请号：US17150658

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Tzu Ang Chao ,  Chao-Ching Cheng ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L23/31 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the etch stop layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

公开(公告)号：US11302695B2

公开(公告)日：2022-04-12

申请号：US16940258

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Ling-Yen Yeh ,  Carlos H. Diaz ,  Tung-Ying Lee

IPC: H01L27/092 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L23/538 ,  H01L29/423 ,  H01L29/778 ,  H01L29/45 ,  H01L27/12 ,  G06F16/955 ,  G06F3/0481 ,  G06F13/00 ,  H04L29/06 ,  H04L67/303 ,  H04L67/306

Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.

公开(公告)号：US11239354B2

公开(公告)日：2022-02-01

申请号：US16926766

申请日：2020-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Chao-Ching Cheng ,  Tzu-Ang Chao ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

公开(公告)号：US20210375934A1

公开(公告)日：2021-12-02

申请号：US17130609

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Georgios Vellianitis

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

公开(公告)号：US20210375933A1

公开(公告)日：2021-12-02

申请号：US17117570

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L21/02

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

公开(公告)号：US20210375888A1

公开(公告)日：2021-12-02

申请号：US17098919

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/786 ,  H01L29/66

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.