公开(公告)号：US20190067478A1

公开(公告)日：2019-02-28

申请号：US15692471

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/167 ,  H01L23/535 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a first fin structure over the base. The semiconductor device structure includes an isolation layer over the base. The first fin structure is partially in the isolation layer. The semiconductor device structure includes a first gate structure over and across the first fin structure. The semiconductor device structure includes a first source structure and a first drain structure on the first fin structure and on two opposite sides of the first gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The semiconductor device structure includes a cap layer covering the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element.

公开(公告)号：US20180138172A1

公开(公告)日：2018-05-17

申请号：US15353933

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Han-Wei WU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

公开(公告)号：US20180083109A1

公开(公告)日：2018-03-22

申请号：US15814129

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Sheng-Chen WANG ,  Wei-Yuan LU ,  Chien-I KUO ,  Li-Li SU ,  Feng-Cheng YANG ,  Yen-Ming CHEN ,  Sai-Hooi YEONG

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/08 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2224/056

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

公开(公告)号：US20170256456A1

公开(公告)日：2017-09-07

申请号：US15061609

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20160322477A1

公开(公告)日：2016-11-03

申请号：US15208393

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract translation: 半导体器件包括用于第一鳍式场效应晶体管（FET）的第一鳍结构。 第一鳍结构包括从基板突出的第一基底层，设置在第一基底层上的第一中间层和设置在第一中间层上的第一沟道层。 第一翅片结构还包括由防止下层氧化的材料制成的第一保护层。 第一沟道层由SiGe制成，第一中间层包括设置在第一基极层上的第一半导体（例如，SiGe）层和设置在第一半导体层上的第二半导体层（例如Si）。 第一保护层覆盖第一基底层的侧壁，第一半导体层的侧壁和第二半导体层的侧壁。