公开(公告)号：US10312072B2

公开(公告)日：2019-06-04

申请号：US16045576

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai

IPC: H01G4/018 ,  H01L21/02 ,  H01L33/00 ,  H01L27/088 ,  H01L29/02

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; and a gate structure engaging a top portion of the fin.

公开(公告)号：US12191371B2

公开(公告)日：2025-01-07

申请号：US17736036

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Jin Cai ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/22 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20240290871A1

公开(公告)日：2024-08-29

申请号：US18657927

申请日：2024-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Kai Su ,  Jin Cai

IPC: H01L29/66 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/24 ,  H01L29/78696

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

公开(公告)号：US12009411B2

公开(公告)日：2024-06-11

申请号：US17874377

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Kai Su ,  Jin Cai

IPC: H01L29/66 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/24 ,  H01L29/78696

Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

公开(公告)号：US11930696B2

公开(公告)日：2024-03-12

申请号：US17308635

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai ,  Sheng-Kai Su

IPC: H10K85/20 ,  H01L21/02 ,  H01L29/06 ,  H10K10/46

CPC classification number: H10K85/221 ,  H01L21/02606 ,  H01L29/0673 ,  H10K10/472 ,  H10K10/474 ,  H10K10/484

Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

公开(公告)号：US11862243B2

公开(公告)日：2024-01-02

申请号：US17876379

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi Wu ,  Win-San Khwa ,  Jin Cai ,  Yu-Sheng Chen

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/0052 ,  G11C2013/0054

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

公开(公告)号：US11855221B2

公开(公告)日：2023-12-26

申请号：US17874466

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/02321 ,  H01L29/517 ,  H01L29/66795

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

公开(公告)号：US11387360B2

公开(公告)日：2022-07-12

申请号：US16874526

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US20200127138A1

公开(公告)日：2020-04-23

申请号：US16255334

申请日：2019-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Chia-Cheng Ho ,  Tzu-Chung Wang ,  Tung Ying Lee ,  Jin Cai ,  Ming-Shiang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US20240250032A1

公开(公告)日：2024-07-25

申请号：US18308355

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Guan-Lin Chen ,  Yu-Xuan Huang ,  Jin Cai

IPC: H01L23/535 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/535 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.