公开(公告)号：US10170317B1

公开(公告)日：2019-01-01

申请号：US15718565

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US20230378360A1

公开(公告)日：2023-11-23

申请号：US18361514

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Hsin-Che Chiang ,  Yu-Chi Pan ,  Chun-Ming Yang ,  Chun-Sheng Liang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L29/42372 ,  H01L21/28556 ,  H01L29/401 ,  H01L21/32134 ,  H01L29/4966

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US20200152772A1

公开(公告)日：2020-05-14

申请号：US16746097

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10541317B2

公开(公告)日：2020-01-21

申请号：US15909847

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10361133B2

公开(公告)日：2019-07-23

申请号：US15707990

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chih-Long Chiang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo Bin Huang

IPC: H01L21/8238 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.