公开(公告)号：US20180175171A1

公开(公告)日：2018-06-21

申请号：US15644600

申请日：2017-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Li-Te LIN ,  Yu-Lien HUANG

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

公开(公告)号：US20240274471A1

公开(公告)日：2024-08-15

申请号：US18626229

申请日：2024-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02263 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact, and a first conductive via. The gate structure is over the semiconductor substrate. The source/drain region is adjacent the gate structure. The source/drain contact is over the source/drain region. The first conductive via is over the source/drain contact. From a top view, the first conductive via has two opposite first long sides and two opposite first short sides connecting the first long sides, and the first short sides are shorter than the first long sides and more curved than the first long sides. From a cross-sectional view, the first long sides of the first conductive via have bottom segments higher than a top surface of the gate structure.

公开(公告)号：US20210013103A1

公开(公告)日：2021-01-14

申请号：US17033256

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.

公开(公告)号：US20200335340A1

公开(公告)日：2020-10-22

申请号：US16921032

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun HUANG ,  Chiu-Hsiang CHEN ,  Ya-Wen YEH ,  Yu-Tien SHEN ,  Po-Chin CHANG ,  Chien Wen LAI ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20200066872A1

公开(公告)日：2020-02-27

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US20190165133A1

公开(公告)日：2019-05-30

申请号：US16192566

申请日：2018-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei JHAN ,  Yi-Lun CHEN ,  Fang-Wei LEE ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.

公开(公告)号：US20190165132A1

公开(公告)日：2019-05-30

申请号：US16136339

申请日：2018-09-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L21/321 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.

公开(公告)号：US20190097056A1

公开(公告)日：2019-03-28

申请号：US16141509

申请日：2018-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L27/12

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20240194480A1

公开(公告)日：2024-06-13

申请号：US18581043

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/02321 ,  H01L21/26586 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/66545

Abstract: A method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. The second dosage source is different from the first dosage source.

公开(公告)号：US20230017512A1

公开(公告)日：2023-01-19

申请号：US17377861

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Pinyen LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Han-yu LIN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/66

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.