公开(公告)号：US10763255B2

公开(公告)日：2020-09-01

申请号：US16103721

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/165 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/205

Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.

公开(公告)号：US10720503B2

公开(公告)日：2020-07-21

申请号：US16103704

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.

公开(公告)号：US10510874B2

公开(公告)日：2019-12-17

申请号：US15883684

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

公开(公告)号：US20180151688A1

公开(公告)日：2018-05-31

申请号：US15409617

申请日：2017-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US09941279B2

公开(公告)日：2018-04-10

申请号：US15226007

申请日：2016-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/308 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  H01L21/3065

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/108 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.

公开(公告)号：US12302630B2

公开(公告)日：2025-05-13

申请号：US18447881

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Jung-Chien Cheng ,  Shi-Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang

IPC: H10D84/83 ,  H01L21/762 ,  H10D30/01 ,  H10D62/10 ,  H10D64/27

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

公开(公告)号：US11942476B2

公开(公告)日：2024-03-26

申请号：US17866365

申请日：2022-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/205

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.

公开(公告)号：US11456368B2

公开(公告)日：2022-09-27

申请号：US16547994

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Huan-Chieh Su ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

公开(公告)号：US11349016B2

公开(公告)日：2022-05-31

申请号：US16910450

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure.

公开(公告)号：US11201225B2

公开(公告)日：2021-12-14

申请号：US16834264

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Guan-Lin Chen ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure.