公开(公告)号：US11488912B2

公开(公告)日：2022-11-01

申请号：US17112029

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Kuan ,  Chih-Teng Liao ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L23/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/24 ,  H01L29/78

Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

公开(公告)号：US09721805B1

公开(公告)日：2017-08-01

申请号：US15223933

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Lee ,  Chen-Wei Pan ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L21/76 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L21/311 ,  H01L21/02129 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/02579 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming first and second fin structures over a semiconductor substrate. Each of the first and second fin structures has an upper portion and a lower portion. The method also includes forming a phosphosilicate glass (PSG) layer surrounding the upper and lower portions of the first fin structure. The method further includes doping the PSG layer to form a doped PSG layer. In addition, the method includes forming a borosilicate glass (BSG) layer surrounding the upper and lower portions of the second fin structure. The BSG layer extends over the doped PSG layer. The method also includes forming an isolation layer over the BSG layer. The method further includes partially etching the isolation layer, the BSG layer and the doped PSG layer to expose the upper portions of the first and second fin structures.

公开(公告)号：US09391072B2

公开(公告)日：2016-07-12

申请号：US14817041

申请日：2015-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Wei Chiu ,  Hsin-Yi Tsai ,  Tzu-Chan Weng ,  Li-Te Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/823814 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.