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    Semiconductor Device With Air Gaps Between Metal Gates And Method Of Forming The Same
    21.
    发明申请
    Semiconductor Device With Air Gaps Between Metal Gates And Method Of Forming The Same 有权

    公开(公告)号：US20220344216A1

    公开(公告)日：2022-10-27

    申请号：US17861679

    申请日：2022-07-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

    IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

    Semiconductor Device with Corner Isolation Protection and Methods of Forming the Same
    22.
    发明申请
    Semiconductor Device with Corner Isolation Protection and Methods of Forming the Same 有权

    公开(公告)号：US20220310783A1

    公开(公告)日：2022-09-29

    申请号：US17213402

    申请日：2021-03-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Pin-Ju Liang ,  Chang-Miao Liu ,  Shih-Hao Lin

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

    Gate Cut Dielectric Feature and Method of Forming the Same
    24.
    发明申请
    Gate Cut Dielectric Feature and Method of Forming the Same 有权

    公开(公告)号：US20210118875A1

    公开(公告)日：2021-04-22

    申请号：US16656609

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

    Abstract: Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

    Transistor Structure and Method With Strain Effect
    25.
    发明申请
    Transistor Structure and Method With Strain Effect 有权

    公开(公告)号：US20210083112A1

    公开(公告)日：2021-03-18

    申请号：US16573898

    申请日：2019-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xusheng Wu ,  Youbo Lin

    IPC: H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66

    Abstract: The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.

    SEMICONDUCTOR DEVICE WITH S/D BOTTOM ISOLATION AND METHODS OF FORMING THE SAME
    26.
    发明申请
    SEMICONDUCTOR DEVICE WITH S/D BOTTOM ISOLATION AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20240379442A1

    公开(公告)日：2024-11-14

    申请号：US18784531

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

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