公开(公告)号：US20200273805A1

公开(公告)日：2020-08-27

申请号：US16283836

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.

公开(公告)号：US20230387028A1

公开(公告)日：2023-11-30

申请号：US18447769

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US11600573B2

公开(公告)日：2023-03-07

申请号：US16452830

申请日：2019-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Yi-Wen Wu ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

公开(公告)号：US20220230978A1

公开(公告)日：2022-07-21

申请号：US17326941

申请日：2021-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Yi-Wen Wu ,  Sheng-Pin Yang ,  Hao-Chun Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48 ,  H01L49/02

Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.

公开(公告)号：US11362010B2

公开(公告)日：2022-06-14

申请号：US16654187

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Liang Lin ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Yi-Wen Wu ,  Techi Wong ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die over a first surface of a redistribution structure. The method also includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element over a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

公开(公告)号：US20210391317A1

公开(公告)日：2021-12-16

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11133265B2

公开(公告)日：2021-09-28

申请号：US16714818

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Yi-Wen Wu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

公开(公告)号：US10068853B2

公开(公告)日：2018-09-04

申请号：US15147909

申请日：2016-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Yi-Wen Wu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

公开(公告)号：US12176337B2

公开(公告)日：2024-12-24

申请号：US17869968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11594484B2

公开(公告)日：2023-02-28

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.