公开(公告)号：US20230377913A1

公开(公告)日：2023-11-23

申请号：US18364588

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  H01L21/265

CPC classification number: H01L21/67098 ,  H01L21/265 ,  H01L21/67196 ,  H01L21/67213 ,  H01L21/67248 ,  H01L21/67207

Abstract: Embodiments of an ion cryo-implantation process utilize a post implantation heating stage to heat the implanted wafer while under the heavy vacuum used during cryo-implantation. The implanted wafer is then transferred to load locks which are held at a lesser vacuum than the heavy vacuum.

公开(公告)号：US20230261048A1

公开(公告)日：2023-08-17

申请号：US17670924

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/66545

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

公开(公告)号：US20230042196A1

公开(公告)日：2023-02-09

申请号：US17670740

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234

Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

公开(公告)号：US20220406774A1

公开(公告)日：2022-12-22

申请号：US17655637

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Bau-Ming Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/36 ,  H01L21/265 ,  H01L21/266

Abstract: A semiconductor structure having doped wells and a method of forming is provided. The doped wells may utilize parallel implantation techniques and tilt implantation techniques to form wells having less lateral diffusion and less vertical doping.

公开(公告)号：US11450757B2

公开(公告)日：2022-09-20

申请号：US17013615

申请日：2020-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Wei-Ting Chien ,  Chih-Pin Tsao ,  Hou-Ju Li ,  Tien-Shun Chang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

公开(公告)号：US09607838B1

公开(公告)日：2017-03-28

申请号：US14859165

申请日：2015-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Hou-Yu Chen ,  Yong-Yan Lu

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20240387279A1

公开(公告)日：2024-11-21

申请号：US18786530

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Shu Ling Liao ,  Fang-Yi Liao ,  Yu-Chang Lin

IPC: H01L21/8234 ,  H01L21/3115 ,  H01L27/088

Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.

公开(公告)号：US20240379751A1

公开(公告)日：2024-11-14

申请号：US18781098

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

公开(公告)号：US20240136228A1

公开(公告)日：2024-04-25

申请号：US18401780

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

公开(公告)号：US11901235B2

公开(公告)日：2024-02-13

申请号：US17824610

申请日：2022-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.