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    FinFET Structures and Methods of Forming the Same
    22.
    发明申请
    FinFET Structures and Methods of Forming the Same 有权

    公开(公告)号：US20210043772A1

    公开(公告)日：2021-02-11

    申请号：US17077383

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

    FinFET structures and methods of forming the same
    25.
    发明授权
    FinFET structures and methods of forming the same 有权

    公开(公告)号：US11563120B2

    公开(公告)日：2023-01-24

    申请号：US17077383

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

    Methods for Forming Contact Plugs with Reduced Corrosion
    26.
    发明申请
    Methods for Forming Contact Plugs with Reduced Corrosion 有权

    公开(公告)号：US20210257254A1

    公开(公告)日：2021-08-19

    申请号：US17234136

    申请日：2021-04-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

    IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/288 ,  H01L29/66

    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

    Semiconductor device and manufacturing method thereof
    29.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10157998B2

    公开(公告)日：2018-12-18

    申请号：US15811374

    申请日：2017-11-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Kuan-Ting Liu

    IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

    Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

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