公开(公告)号：US20180149959A1

公开(公告)日：2018-05-31

申请号：US15670183

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/42 ,  G03F1/26 ,  G03F1/48

CPC classification number: G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/50 ,  G03F1/54

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.

公开(公告)号：US20180059534A1

公开(公告)日：2018-03-01

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  H01L21/033

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

公开(公告)号：US20180059531A1

公开(公告)日：2018-03-01

申请号：US15597992

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee

IPC: G03F1/26 ,  G03F7/20 ,  G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  H01L21/308 ,  H01L21/266

CPC classification number: G03F1/26 ,  G03F1/34 ,  G03F1/38 ,  G03F1/80

Abstract: The present disclosure provides a phase shift mask. The phase shift mask includes a transparent substrate; an etch stop layer disposed on the substrate; and a tunable transparent material layer disposed on the etch stop layer and patterned to have an opening, wherein the tunable transparent material layer is designed to provide phase shift and has a transmittance greater than 90%.

公开(公告)号：US11846880B2

公开(公告)日：2023-12-19

申请号：US17744567

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.

公开(公告)号：US20230367205A1

公开(公告)日：2023-11-16

申请号：US18360030

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin

IPC: G03F1/64 ,  G03F7/00

CPC classification number: G03F1/64 ,  G03F7/70733

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process. The apparatus includes a mask defining a circuit pattern to be transferred. The apparatus further includes a pellicle including a pattern formed in a first surface, wherein the pellicle is attached to the mask at the first surface. The apparatus also includes an adhesive material layer disposed between the mask and the first surface. The pattern may include a plurality of capillaries. Each capillary of the plurality of capillaries may have a dimension in a plane of the first surface between about 1 µm and about 500 µm. Each capillary of the plurality of capillaries may have a ratio of depth to width greater than or equal to about 100. The adhesive material layer may include an adhesive having a glass transition temperature (Tg) greater than room temperature.

公开(公告)号：US11656544B2

公开(公告)日：2023-05-23

申请号：US17728945

申请日：2022-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Yue Lin

IPC: G03F1/64 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F7/70983 ,  G03F7/2004

Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.

公开(公告)号：US11526073B2

公开(公告)日：2022-12-13

申请号：US17692912

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po Hsuan Li ,  Yu-Ting Lin ,  Yun-Yue Lin ,  Huai-Tei Yang

IPC: G03F1/62 ,  G03F7/20

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

公开(公告)号：US20220357649A1

公开(公告)日：2022-11-10

申请号：US17815070

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin

IPC: G03F1/64 ,  G03F7/20

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process. The apparatus includes a mask defining a circuit pattern to be transferred. The apparatus further includes a pellicle including a pattern formed in a first surface, wherein the pellicle is attached to the mask at the first surface. The apparatus also includes an adhesive material layer disposed between the mask and the first surface. The pattern may include a plurality of capillaries. Each capillary of the plurality of capillaries may have a dimension in a plane of the first surface between about 1 μm and about 500 μm. Each capillary of the plurality of capillaries may have a ratio of depth to width greater than or equal to about 100. The adhesive material layer may include an adhesive having a glass transition temperature (Tg) greater than room temperature.

公开(公告)号：US11314169B2

公开(公告)日：2022-04-26

申请号：US16885126

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Yue Lin

IPC: G03F7/20 ,  G03F1/64

Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.

公开(公告)号：US11137684B2

公开(公告)日：2021-10-05

申请号：US16719118

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/54

Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.