公开(公告)号：US10012899B2

公开(公告)日：2018-07-03

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  G03F1/64 ,  H01L21/033 ,  C23C14/16 ,  C23C16/26 ,  C23C28/00 ,  C23C14/18

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

公开(公告)号：US20170372917A1

公开(公告)日：2017-12-28

申请号：US15194631

申请日：2016-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chue San Yoo

IPC: H01L21/311 ,  H01J37/32 ,  H01L23/544 ,  H01L21/68 ,  H01L21/67 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/681 ,  H01L23/544 ,  H01L2223/54426

Abstract: A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided.

公开(公告)号：US11289341B2

公开(公告)日：2022-03-29

申请号：US16587335

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chue San Yoo

IPC: H01L21/00 ,  H01L21/311 ,  H01L23/544 ,  H01L21/67 ,  H01L21/68 ,  H01J37/32

Abstract: A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided.

公开(公告)号：US20200027747A1

公开(公告)日：2020-01-23

申请号：US16587335

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chue San Yoo

IPC: H01L21/311 ,  H01L23/544 ,  H01L21/67 ,  H01L21/68 ,  H01J37/32

Abstract: A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided.

公开(公告)号：US20180059534A1

公开(公告)日：2018-03-01

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  H01L21/033

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.