公开(公告)号：US12125747B2

公开(公告)日：2024-10-22

申请号：US17814737

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76879 ,  H01L21/2254 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76882 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/31122 ,  H01L21/76831 ,  H01L29/456

Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US12087627B2

公开(公告)日：2024-09-10

申请号：US17870213

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Hsun Lin ,  Che-Chih Hsu ,  Wen-Chu Huang ,  Chinyu Su ,  Yen-Yu Chen ,  Wei-Chun Hua ,  Wen Han Hung

IPC: H01L21/76 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522 ,  H01L23/64 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L21/76877 ,  H01L21/0276 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L28/10

Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

公开(公告)号：US20240167149A1

公开(公告)日：2024-05-23

申请号：US18424531

申请日：2024-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: C23C16/02 ,  C23C14/02 ,  C23C14/34 ,  C23C16/34 ,  C23C16/458 ,  C23C16/46

CPC classification number: C23C16/0245 ,  C23C14/021 ,  C23C14/34 ,  C23C16/34 ,  C23C16/4583 ,  C23C16/463 ,  H01L2224/77185

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

公开(公告)号：US11822237B2

公开(公告)日：2023-11-21

申请号：US17071004

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Jia-Lin Wei ,  Yen-Yu Chen ,  Jr-Hung Li ,  Yahru Cheng ,  Chi-Ming Yang ,  Tze-Liang Lee ,  Ching-Yu Chang

IPC: G03F7/004 ,  H01L21/033 ,  G03F7/00

CPC classification number: G03F7/004 ,  G03F7/0035 ,  H01L21/0332

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20230369048A1

公开(公告)日：2023-11-16

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin WEI ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/00 ,  G03F1/22

CPC classification number: H01L21/0332 ,  H01L21/3081 ,  G03F7/70033 ,  G03F1/22 ,  H01L21/0334

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US11732379B2

公开(公告)日：2023-08-22

申请号：US16901967

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zong-Kun Lin ,  Hsuan-Chih Chu ,  Chien-Hsun Pan ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: B01D61/18 ,  B01D63/16 ,  C25D21/06

CPC classification number: C25D21/06 ,  B01D61/18 ,  B01D63/16 ,  B01D2311/2642 ,  B01D2313/18 ,  B01D2313/22 ,  B01D2313/44

Abstract: The treatment system provides a feature that may reduce cost of the electrochemical plating process by reusing the virgin makeup solution in the spent electrochemical plating bath. The treatment system provides a rotating filter shaft which receives the spent electrochemical plating bath and captures the additives and by-products created by the additives during the electrochemical plating process. To capture the additives and the by-products, the rotating filter shaft includes one or more types of membranes. Materials such as semi-permeable membrane are used to capture the used additives and by-products in the spent electrochemical plating bath. The treatment system may be equipped with an electrochemical sensor to monitor a level of additives in the filtered electrochemical plating bath.

公开(公告)号：US11725270B2

公开(公告)日：2023-08-15

申请号：US17115700

申请日：2020-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsi Wang ,  Yen-Yu Chen ,  Yi-Chih Chen ,  Shih Wei Bih

IPC: C23C14/34 ,  H01L21/768 ,  H01J37/34 ,  C23C14/14 ,  H01L21/285 ,  H01L23/532

CPC classification number: C23C14/3407 ,  C23C14/14 ,  C23C14/3464 ,  H01J37/3429 ,  H01J37/3435 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

公开(公告)号：US11682639B2

公开(公告)日：2023-06-20

申请号：US17383215

申请日：2021-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Yi-Ming Dai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L24/03 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/3171 ,  H01L23/5226 ,  H01L24/08

Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

公开(公告)号：US11610822B2

公开(公告)日：2023-03-21

申请号：US16925893

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033

Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

公开(公告)号：US20220367606A1

公开(公告)日：2022-11-17

申请号：US17815524

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Anhao CHENG ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.