公开(公告)号：US11830808B2

公开(公告)日：2023-11-28

申请号：US17739384

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20220262726A1

公开(公告)日：2022-08-18

申请号：US17739384

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US11049811B2

公开(公告)日：2021-06-29

申请号：US16232921

申请日：2018-12-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Lin Teng ,  Jung-Hsun Tsai ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/51 ,  H01L29/66 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/45 ,  H01L29/78

摘要： A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

公开(公告)号：US20170256491A1

公开(公告)日：2017-09-07

申请号：US15601305

申请日：2017-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-l Bao

IPC分类号： H01L23/522 ,  H01L21/02

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US20170125340A1

公开(公告)日：2017-05-04

申请号：US14928916

申请日：2015-10-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung-Hsun Tsai ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao ,  Chien-Hua Huang

IPC分类号： H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

摘要： The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

公开(公告)号：US20170103949A1

公开(公告)日：2017-04-13

申请号：US14879259

申请日：2015-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Lin Teng ,  Jung-Hsun Tsai ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/532 ,  H01L21/283 ,  H01L21/31 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L29/51 ,  H01L29/45 ,  H01L23/528 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5329 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/32051 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

摘要： A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

公开(公告)号：US09165822B2

公开(公告)日：2015-10-20

申请号：US13874893

申请日：2013-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.

摘要翻译： 公开了一种半导体器件结构及其形成方法。 实施例是一种形成半导体器件的方法，所述方法包括在衬底上形成第一导电线，并且在第一导电线的顶表面和侧壁上保形地形成第一电介质层，第一介电层具有第一 孔隙率百分比和第一碳浓度。 该方法还包括在第一介电层上形成第二介电层，第二介电层具有第二孔隙率和第二碳浓度，第二孔隙率与第一孔隙率不同，第二碳浓度小于 第一个碳浓度。

公开(公告)号：US20140252624A1

公开(公告)日：2014-09-11

申请号：US13874893

申请日：2013-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.

摘要翻译： 公开了一种半导体器件结构及其形成方法。 实施例是一种形成半导体器件的方法，所述方法包括在衬底上形成第一导电线，并且在第一导电线的顶表面和侧壁上保形地形成第一电介质层，第一介电层具有第一 孔隙率百分比和第一碳浓度。 该方法还包括在第一介电层上形成第二介电层，第二介电层具有第二孔隙率和第二碳浓度，第二孔隙率与第一孔隙率不同，第二碳浓度小于 第一个碳浓度。

公开(公告)号：US12068248B2

公开(公告)日：2024-08-20

申请号：US17217694

申请日：2021-03-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226

摘要： An interconnect structure includes a dielectric layer, a conductive feature, a conductive layer, a capping layer, a support layer and an etch stop layer. The conductive feature is disposed in the dielectric layer. A first portion of the conductive layer is disposed over the first conductive feature, and a second portion of the conductive layer is disposed over the dielectric layer. A first portion of the capping layer is in contact with the first portion of the conductive layer, a second portion of the capping layer is in contact with the second portion of the conductive layer, and a third portion of the capping layer is in contact with the dielectric layer. An air gap is defined by the support layer and the capping layer. The etch stop layer is disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer.

公开(公告)号：US11854963B2

公开(公告)日：2023-12-26

申请号：US17346209

申请日：2021-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shao-Kuan Lee ,  Kuang-Wei Yang ,  Cherng-Shiaw Tsai ,  Cheng-Chin Lee ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/532

摘要： An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.