-
公开(公告)号：US11177365B2
公开(公告)日：2021-11-16
申请号：US16695006
申请日：2019-11-25
发明人： Shih Wei Bih , Chun-Chih Lin , Yen-Yu Chen
IPC分类号： H01L29/66 , H01L21/28 , H01L21/321 , H01L21/326 , H01L29/49 , H01L29/78 , H01L29/423 , H01L29/51 , H01L29/417 , H01L29/08
摘要： A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.
-
公开(公告)号：US11164957B2
公开(公告)日：2021-11-02
申请号：US16694971
申请日：2019-11-25
发明人： Shih Wei Bih , Chun-Chih Lin , Yen-Yu Chen
IPC分类号： H01L29/66 , H01L21/28 , H01L21/321 , H01L21/326 , H01L29/49 , H01L29/78 , H01L29/423 , H01L29/51 , H01L29/417 , H01L29/08
摘要： A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.
-
公开(公告)号：US10752995B2
公开(公告)日：2020-08-25
申请号：US15442467
申请日：2017-02-24
发明人： Ke-Chih Liu , Chia-Ming Tsai , Yen-Yu Chen , Yueh-Ching Pai , Yu-Min Chang
摘要： A method includes applying a first amount of heat to a vapor region of a precursor canister, measuring an indication of saturated vapor pressure within the vapor region during the applying the first amount of heat, and applying a second amount of heat to the vapor region of the precursor canister, the second amount of heat being adjusted from the first amount of heat based on the indication of saturated vapor pressure.
-
公开(公告)号：US10186602B2
公开(公告)日：2019-01-22
申请号：US15277777
申请日：2016-09-27
IPC分类号： H01L29/66 , H01L29/06 , H01L21/762 , H01L21/02 , H01L21/321 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L21/8238 , H01L29/78
摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.
-
公开(公告)号：US09472652B2
公开(公告)日：2016-10-18
申请号：US14137725
申请日：2013-12-20
IPC分类号： H01L27/088 , H01L29/66 , H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/0228 , H01L21/32105 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/1054 , H01L29/7853
摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.
摘要翻译： 本发明涉及鳍状场效应晶体管（FinFET）。 示例性FinFET包括包含主表面的衬底; 从所述主表面突出的鳍结构，包括包括具有第一晶格常数的第一半导体材料的上部，其中所述上部包括具有第一宽度的第一基本垂直部分和具有小于所述第一宽度的第二宽度的第二基本垂直部分 第一宽度在第一基本竖直部分上; 以及下部，包括具有小于所述第一晶格常数的第二晶格常数的第二半导体材料，其中所述下部的顶表面具有小于所述第一宽度的第三宽度; 以及覆盖所述第二基本垂直部分的栅极结构。
-
26.发明授权Method for tuning threshold voltage of semiconductor device with metal gate structure 有权用金属栅极结构调整半导体器件的阈值电压的方法公开(公告)号：US09362385B2
公开(公告)日：2016-06-07
申请号：US14132901
申请日：2013-12-18
发明人： Chung-Liang Cheng , Yen-Yu Chen , Wei-Jen Chen , Chang-Sheng Lee , Wei Zhang
IPC分类号： H01L21/316 , H01L29/66 , H01L29/06
CPC分类号： H01L29/66795 , H01L29/0673 , H01L29/66545
摘要： A method for manufacturing a metal gate structure includes forming a high-k dielectric layer in a gate trench; forming an etch stop over the high-k dielectric layer; forming a work function adjusting layer over the etch stop by forming a tri-layer by an atomic layer deposition (ALD) operation with a sequence of a grain boundary engineering layer configured to allow a dopant atom to penetrate there through, a doping layer configured to provide the dopant atom to the grain boundary engineering layer, and a capping layer configured to prevent the doping layer from oxidation; and filling metal to level up the gate trench. The grain boundary engineering layer is prepared by the ALD operation under various temperatures such as from about 200 to about 350 degrees Celsius.
摘要翻译： 一种制造金属栅极结构的方法包括在栅极沟槽中形成高k电介质层; 在高k电介质层上形成蚀刻停止层; 通过用原子层沉积（ALD）操作形成三层，通过构造成允许掺杂剂原子穿过其中的晶界工程层的序列，在蚀刻停止层上形成功函数调整层，掺杂层被配置为 将所述掺杂剂原子提供给所述晶界工程层，以及覆盖层，其被配置为防止所述掺杂层氧化; 并填充金属以平衡栅极沟槽。 通过在各种温度例如约200至约350摄氏度的ALD操作来制备晶界工程层。
-
公开(公告)号：US20160005825A1
公开(公告)日：2016-01-07
申请号：US14853587
申请日：2015-09-14
IPC分类号： H01L29/417 , H01L21/8234 , H01L21/285
CPC分类号： H01L29/7851 , H01L21/28525 , H01L21/28568 , H01L21/324 , H01L21/76224 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L27/0886 , H01L29/165 , H01L29/41791 , H01L29/45 , H01L29/49 , H01L29/495 , H01L29/4958 , H01L29/518 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.
-
公开(公告)号：US20230032857A1
公开(公告)日：2023-02-02
申请号：US17581958
申请日：2022-01-23
发明人： Chia-Hsi Wang , Yen-Yu Chen , Jen-Hao Chien
IPC分类号： C23C16/455 , G01N23/2273 , C23C16/38 , C23C16/52
摘要： A method is provided. The method includes the following steps: introducing a first physical vapor deposition (PVD) target and a second PVD target in a PVD system, the first PVD target containing a boron-containing cobalt iron alloy (FeCoB) with an initial boron concentration, and the second PVD target containing boron; determining parameters of the PVD system based on a target boron concentration larger than the initial boron concentration; and depositing a FeCoB film on a substrate according to the parameters of the PVD system.
-
公开(公告)号：US20220223536A1
公开(公告)日：2022-07-14
申请号：US17308321
申请日：2021-05-05
发明人： Wen-Chun Wang , Tzy-Kuang Lee , Chih-Hsien Lin , Ching-Hung Kao , Yen-Yu Chen
IPC分类号： H01L23/532 , H01L23/522 , H01L23/31 , H01L23/29 , H01L23/528 , H01L21/56 , H01L21/768
摘要： Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.
-
公开(公告)号：US20220154330A1
公开(公告)日：2022-05-19
申请号：US17096962
申请日：2020-11-13
发明人： Wen-Hao Cheng , Hsuan-Chih Chu , Yen-Yu Chen
摘要： A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.018 秒)