公开(公告)号：US20100123184A1

公开(公告)日：2010-05-20

申请号：US12618119

申请日：2009-11-13

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

公开(公告)号：US08680612B2

公开(公告)日：2014-03-25

申请号：US13601400

申请日：2012-08-31

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

摘要： According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side.

摘要翻译： 根据一个实施例，半导体器件包括由半导体衬底中的隔离区分隔开的元件区域，以及通过沿预定方向的栅极沟槽隔离形成在元件区域的表面层中的源极区域和漏极区域 跨越元素区域。 半导体器件包括通过在栅极沟槽中至少部分地嵌入栅极电介质膜而形成为达到比源极区域和漏极区域更深的位置的栅电极。 与栅极电介质膜接触的漏极区域中的界面包括向栅电极侧突出的突起。

公开(公告)号：US08614477B2

公开(公告)日：2013-12-24

申请号：US13364588

申请日：2012-02-02

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

公开(公告)号：US20110284996A1

公开(公告)日：2011-11-24

申请号：US13109086

申请日：2011-05-17

申请人： Takashi Kurusu ,  Takashi Izumida ,  Hiroyoshi Tanimoto ,  Nobutoshi Aoki

发明人： Takashi Kurusu ,  Takashi Izumida ,  Hiroyoshi Tanimoto ,  Nobutoshi Aoki

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。 该装置还包括多个绝缘体，其设置成埋在多个互连件之间。 此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数 。

公开(公告)号：US08035199B2

公开(公告)日：2011-10-11

申请号：US12402093

申请日：2009-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/06

CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/66795

摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜 含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区 半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

公开(公告)号：US07923788B2

公开(公告)日：2011-04-12

申请号：US12207121

申请日：2008-09-09

申请人： Tatsuya Ohguro ,  Takashi Izumida ,  Satoshi Inaba ,  Kimitoshi Okano ,  Nobutoshi Aoki

发明人： Tatsuya Ohguro ,  Takashi Izumida ,  Satoshi Inaba ,  Kimitoshi Okano ,  Nobutoshi Aoki

IPC分类号： H01L21/28 ,  H01L29/08

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.

摘要翻译： 半导体器件具有形成在半导体衬底上的多个翅片以彼此分离，第一接触区域与多个翅片的共同的一端侧连接;第二接触区域，其共同连接多个翅片的另一端侧; 翅片，栅电极，通过在其间夹有栅极绝缘膜而布置成与所述多个翅片的至少两个侧表面相对，在所述第一触点更靠近所述第一触点的一侧包括所述第一接触区域和所述多个翅片的源电极 区域，以及包括第二接触区域的漏电极和在比栅电极更靠近第二接触的一侧的多个翅片。 漏极区域中的每个鳍​​片的电阻Rd与源极区域中的每个鳍​​片的电阻Rs的比Rd / Rs大于1。

公开(公告)号：US20090101960A1

公开(公告)日：2009-04-23

申请号：US12248483

申请日：2008-10-09

申请人： Nobutoshi AOKI ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

发明人： Nobutoshi AOKI ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

IPC分类号： H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11529 ,  H01L27/11524 ,  H01L27/11526

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

公开(公告)号：US20120146128A1

公开(公告)日：2012-06-14

申请号：US13364588

申请日：2012-02-02

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L27/088

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

公开(公告)号：US20120003801A1

公开(公告)日：2012-01-05

申请号：US13224449

申请日：2011-09-02

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/66795

摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜 含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区 半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

公开(公告)号：US20110068401A1

公开(公告)日：2011-03-24

申请号：US12881415

申请日：2010-09-14

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Yoshiaki Asao ,  Satoshi Inaba

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Yoshiaki Asao ,  Satoshi Inaba

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/66795

摘要： A semiconductor device of an embodiment includes a substrate and a plurality of fins formed on the substrate. The plurality of fins is arranged so that a first distance and a second distance narrower than the first distance are repeated. In addition, the plurality of fins include a semiconductor region in which an impurity concentration of lower portions of side surfaces facing each other in sides forming the first distance is higher than an impurity concentration of lower portions of side surfaces facing each other in sides forming the second distance.

摘要翻译： 实施例的半导体器件包括基板和形成在基板上的多个翅片。 多个翅片被布置成使得比第一距离窄的第一距离和第二距离被重复。 另外，多个散热片包括半导体区域，其中在形成第一距离的侧面中彼此面对的侧面的下部的杂质浓度高于形成第一距离的侧面彼此相对的侧表面的下部的杂质浓度 第二距离。