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35 条记录 (耗时 0.051 秒)

    Semiconductor device and a method of manufacturing the same
    23.
    发明授权
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07759209B2

    公开(公告)日：2010-07-20

    申请号：US11700865

    申请日：2007-02-01

    申请人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

    发明人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/42344

    摘要： A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.

    摘要翻译： 存储单元具有通过栅极绝缘膜设置在半导体衬底的主表面上的控制栅极电极，沿着控制栅电极的侧表面和半导体衬底的主表面设置的ONO膜，设置在栅极绝缘膜上的存储栅电极 控制栅电极的侧表面以及通过ONO膜在半导体衬底的主表面上。 控制栅电极和存储栅电极在其上部分别形成有硅化物膜和通过硅化物膜的表面氧化形成的绝缘膜。

    Semiconductor device and a method of manufacturing the same
    24.
    发明申请
    Semiconductor device and a method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20070215930A1

    公开(公告)日：2007-09-20

    申请号：US11700865

    申请日：2007-02-01

    申请人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

    发明人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/42344

    摘要： A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.

    摘要翻译： 存储单元具有通过栅极绝缘膜设置在半导体衬底的主表面上的控制栅极电极，沿着控制栅电极的侧表面和半导体衬底的主表面设置的ONO膜，设置在栅极绝缘膜上的存储栅电极 控制栅电极的侧表面以及通过ONO膜在半导体衬底的主表面上。 控制栅电极和存储栅电极在其上部分别形成有硅化物膜和通过硅化物膜的表面氧化形成的绝缘膜。

    Method of manufacturing a semiconductor device
    25.
    发明申请
    Method of manufacturing a semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20070269972A1

    公开(公告)日：2007-11-22

    申请号：US11797588

    申请日：2007-05-04

    申请人： Yoshiyuki Kawashima ,  Yasushi Ishii ,  Koichi Toba ,  Satoru Machida ,  Takashi Hashimoto

    发明人： Yoshiyuki Kawashima ,  Yasushi Ishii ,  Koichi Toba ,  Satoru Machida ,  Takashi Hashimoto

    IPC分类号： H01L21/44

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/792

    摘要： Provided is a method of manufacturing a semiconductor device having an ONO film composed of a bottom silicon oxide film, a silicon nitride film and a top silicon oxide film over a substrate. The top silicon oxide film of the ONO film is formed in the following manner. A silicon oxide film is formed over the silicon nitride film, and then a hydrogen gas and an oxygen gas are reacted over the silicon nitride film by heating the silicon nitride film (substrate) while reducing the pressure from the atmospheric pressure to grow the silicon oxide film into the top silicon oxide film. According to the present invention, a silicon oxide film having good uniformity and fewer defects can be formed over a silicon-containing underlayer.

    摘要翻译： 提供一种制造半导体器件的方法，该半导体器件具有在基底上的由底部氧化硅膜，氮化硅膜和顶部氧化硅膜构成的ONO膜。 ONO膜的顶部氧化硅膜以如下方式形成。 在氮化硅膜上形成氧化硅膜，然后通过加热氮化硅膜（衬底）同时使氢气和氧气在氮化硅膜上反应，同时降低大气压力，使氧化硅生长 胶片进入顶部氧化硅膜。 根据本发明，可以在含硅底层上形成均匀性好，缺陷少的氧化硅膜。

    IGBT with a built-in-diode
    27.
    发明授权
    IGBT with a built-in-diode 有权
    IGBT内置二极管

    公开(公告)号：US09412737B2

    公开(公告)日：2016-08-09

    申请号：US14888291

    申请日：2013-05-23

    申请人： Jun Saito ,  Satoru Machida ,  Yusuke Yamashita

    发明人： Jun Saito ,  Satoru Machida ,  Yusuke Yamashita

    IPC分类号： H01L29/732 ,  H01L27/07 ,  H01L29/739 ,  H01L29/872 ,  H01L29/06 ,  H01L29/36 ,  H01L29/423

    CPC分类号： H01L27/0716 ,  H01L27/0727 ,  H01L27/0766 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/872

    摘要： When an IGBT has a barrier layer 10 that separates an upper body region 8a from a lower body region 8b, conductivity modulation is enhanced and on-resistance decreases. When the IGBT also has a Schottky contact region 6 that extends to reach the barrier layer 10, a diode structure can be obtained. In this case, however, a saturation current increases as well as short circuit resistance decreases. The Schottky contact region 6 is separated from the emitter region 4 by the upper body region 8a. By selecting an impurity concentration in the region 8a, an increase in a saturation current can be avoided. Alternatively, a block structure that prevents a depletion layer extending from the region 6 into the region 8a from joining a depletion layer extending from the region 4 into the region 8a may be provided in an area separating the region 6 from the region 4.

    摘要翻译： 当IGBT具有将上部区域8a与下部主体区域8b分隔开的阻挡层10时，电导率调制增强，导通电阻降低。 当IGBT也具有延伸到达阻挡层10的肖特基接触区域6时，可以获得二极管结构。 然而，在这种情况下，饱和电流增加以及短路电阻降低。 肖特基接触区域6通过上体区域8a与发射极区域4分离。 通过选择区域8a中的杂质浓度，可以避免饱和电流的增加。 或者，可以在将区域6与区域4分离的区域中设置防止从区域6延伸到区域8a中的耗尽层与从区域4延伸到区域8a的耗尽层连接的块结构。

    Semiconductor device
    28.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09153576B2

    公开(公告)日：2015-10-06

    申请号：US14584793

    申请日：2014-12-29

    申请人： Hiroshi Hosokawa ,  Yusuke Yamashita ,  Satoru Machida

    发明人： Hiroshi Hosokawa ,  Yusuke Yamashita ,  Satoru Machida

    IPC分类号： H01L27/06 ,  H01L29/739

    CPC分类号： H01L27/0664 ,  H01L29/1095 ,  H01L29/7391 ,  H01L29/7397

    摘要： A semiconductor substrate comprises an IGBT region and a diode region. The IGBT region comprises: an n-type emitter region; a p-type IGBT body region; an n-type IGBT barrier region; an n-type IGBT drift region; a p-type collector region; a first trench; a first insulating layer; and a first gate electrode. The diode region comprises: a p-type diode top body region; an n-type diode barrier region; a p-type diode bottom body region; an n-type cathode region; a second trench; a second insulating layer; and a second gate electrode. An n-type impurity density of a specific part of the diode barrier region making contact with the second insulating layer is higher than an n-type impurity density of the IGBT barrier region.

    摘要翻译： 半导体基板包括IGBT区域和二极管区域。 IGBT区域包括：n型发射极区域; p型IGBT体区域; n型IGBT势垒区域; n型IGBT漂移区; p型集电极区域; 第一个沟槽 第一绝缘层; 和第一栅电极。 二极管区域包括：p型二极管顶体区域; n型二极管阻挡区域; p型二极管底部区域; n型阴极区域; 第二个沟槽 第二绝缘层; 和第二栅电极。 与第二绝缘层接触的二极管阻挡区域的特定部分的n型杂质浓度高于IGBT阻挡区域的n型杂质浓度。

    Reverse conducting IGBT
    29.
    发明授权
    Reverse conducting IGBT 有权
    反向导通IGBT

    公开(公告)号：US09099521B2

    公开(公告)日：2015-08-04

    申请号：US14182923

    申请日：2014-02-18

    申请人： Yusuke Yamashita ,  Satoru Machida ,  Jun Saito

    发明人： Yusuke Yamashita ,  Satoru Machida ,  Jun Saito

    IPC分类号： H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/10

    CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/8611

    摘要： A reverse conducting IGBT that includes an insulated gate; a semiconductor layer having a first conductivity type drift region, a second conductivity type body region, a first conductivity type emitter region, and a second conductivity type intermediate region; and an emitter electrode provided on a surface of the semiconductor layer. The first conductivity type drift region of the semiconductor layer contacts the insulated gate. The second conductivity type body region of the semiconductor layer is provided on the drift region and contacts the insulated gate. The first conductivity type emitter region of the semiconductor layer is provided on the body region and contacts the insulated gate. The second conductivity type intermediate region of the semiconductor layer is provided on the emitter region and is interposed between the emitter region and the emitter electrode.

    摘要翻译： 包括绝缘栅极的反向导通IGBT; 具有第一导电类型漂移区域，第二导电类型体区域，第一导电类型发射极区域和第二导电类型中间区域的半导体层; 以及设置在半导体层的表面上的发射电极。 半导体层的第一导电型漂移区域与绝缘栅极接触。 半导体层的第二导电类型体区设置在漂移区上并与绝缘栅接触。 半导体层的第一导电型发射极区域设置在主体区域上并与绝缘栅极接触。 半导体层的第二导电类型中间区域设置在发射极区域上并且插入在发射极区域和发射极电极之间。

    INSULATED-GATE BIPOLAR TRANSISTOR
    30.
    发明申请
    INSULATED-GATE BIPOLAR TRANSISTOR 有权
    绝缘栅双极晶体管

    公开(公告)号：US20140054645A1

    公开(公告)日：2014-02-27

    申请号：US14002752

    申请日：2012-03-07

    申请人： Jun Saito ,  Satoru Machida

    发明人： Jun Saito ,  Satoru Machida

    IPC分类号： H01L29/423 ,  H01L29/739

    CPC分类号： H01L29/423 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7397

    摘要： In an IGBT, a trench extending in a bent shape to have a corner is formed in an upper surface of a semiconductor substrate. The inside of the trench is covered with an insulating film. A gate is placed inside the trench. An emitter and a collector are formed on an upper surface and a lower surface of the semiconductor substrate, respectively. An emitter region, a body region, a drift region, and a collector region are formed in the semiconductor substrate. The emitter region is formed of an n-type semiconductor, is in contact with the insulating film, and is in ohmic contact with the emitter electrode. The body region is formed of a p-type semiconductor, is in contact with the insulating film below the emitter region, is in contact with the insulating film of an inner corner portion of the trench, and is in ohmic contact with the emitter electrode.

    摘要翻译： 在IGBT中，在半导体基板的上表面形成有以弯曲形状延伸成具有角部的沟槽。 沟槽的内部覆盖有绝缘膜。 一个门被放置在沟槽内。 分别在半导体衬底的上表面和下表面上形成发射极和集电极。 在半导体衬底中形成发射极区域，体区域，漂移区域和集电极区域。 发射极区由n型半导体形成，与绝缘膜接触，与发射电极欧姆接触。 体区域由p型半导体形成，与发射极区域下方的绝缘膜接触，与沟槽的内角部分的绝缘膜接触，并与发射极电极欧姆接触。