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    Copper electrodeposition in microelectronics
    21.
    发明申请
    Copper electrodeposition in microelectronics 有权
    铜电沉积在微电子学

    公开(公告)号：US20060141784A1

    公开(公告)日：2006-06-29

    申请号：US11272999

    申请日：2005-11-14

    申请人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

    发明人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

    IPC分类号： C25C1/12 ,  H01L21/44

    CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/12 ,  C25D7/123 ,  H01L21/76877

    摘要： An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

    摘要翻译： 一种用于在具有亚微米尺寸互连特征的半导体集成电路基板上电解电镀Cu的电解电镀方法和组合物。 该组合物包含Cu离子源和包含聚醚基团的抑制剂化合物。 该方法包括以超填充速度的快速自下而上沉积来超填充，通过其从特征的底部到特征的顶部开口的垂直方向上的Cu沉积基本上大于侧壁上的Cu沉积。

    Copper electrodeposition in microelectronics
    23.
    发明授权
    Copper electrodeposition in microelectronics 有权
    铜电沉积在微电子学

    公开(公告)号：US07303992B2

    公开(公告)日：2007-12-04

    申请号：US11272999

    申请日：2005-11-14

    申请人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

    发明人： Vincent Paneccasio ,  Xuan Lin ,  Paul Figura ,  Richard Hurtubise

    IPC分类号： H01L21/31

    CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/12 ,  C25D7/123 ,  H01L21/76877

    摘要： An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

    摘要翻译： 一种用于在具有亚微米尺寸互连特征的半导体集成电路基板上电解电镀Cu的电解电镀方法和组合物。 该组合物包含Cu离子源和包含聚醚基团的抑制剂化合物。 该方法包括以超填充速度的快速自下而上沉积来超填充，通过其从特征的底部到特征的顶部开口的垂直方向上的Cu沉积基本上大于侧壁上的Cu沉积。

    DEFECT REDUCTION IN ELECTRODEPOSITED COPPER FOR SEMICONDUCTOR APPLICATIONS
    25.
    发明申请
    DEFECT REDUCTION IN ELECTRODEPOSITED COPPER FOR SEMICONDUCTOR APPLICATIONS 有权
    用于半导体应用的电沉积铜中的缺陷减少

    公开(公告)号：US20080121527A1

    公开(公告)日：2008-05-29

    申请号：US11971061

    申请日：2008-01-08

    申请人： John Commander ,  Richard Hurtubise ,  Vincent Paneccasio ,  Xuan Lin ,  Kshama Jirage

    发明人： John Commander ,  Richard Hurtubise ,  Vincent Paneccasio ,  Xuan Lin ,  Kshama Jirage

    IPC分类号： C25D7/12

    CPC分类号： C25D7/123 ,  C25D3/38 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    摘要： A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

    摘要翻译： 一种用于将铜沉积物电镀到具有亚微米尺寸特征的半导体集成电路器件衬底上的方法，以及用于形成相应的电镀浴的浓缩物。 将衬底浸入由包括离子铜和有效量的缺陷还原剂的浓缩物形成的电镀浴中，并将铜沉积物从浴中电镀到衬底上以填充亚微米尺寸的浮雕。 发生由于不均匀生长引起的超填充，表面粗糙度和空隙的突出缺陷的发生，并且提高了晶片上的宏观平面度。