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    Charge-trapping memory device and methods for operating and manufacturing the cell
    21.
    发明申请
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US20060091448A1

    公开(公告)日：2006-05-04

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号：US20060065921A1

    公开(公告)日：2006-03-30

    申请号：US10952233

    申请日：2004-09-28

    申请人： Josef Willer ,  Thomas Mikolajick

    发明人： Josef Willer ,  Thomas Mikolajick

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/792

    摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

    摘要翻译： 位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。 至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。 存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。 它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

    Method for forming a semiconductor product and semiconductor product
    23.
    发明授权
    Method for forming a semiconductor product and semiconductor product 失效
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US07521351B2

    公开(公告)日：2009-04-21

    申请号：US11172366

    申请日：2005-06-30

    申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

    摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

    Method for forming a semiconductor product and semiconductor product
    24.
    发明申请
    Method for forming a semiconductor product and semiconductor product 审中-公开
    用于形成半导体产品和半导体产品的方法

    公开(公告)号：US20070077748A1

    公开(公告)日：2007-04-05

    申请号：US11241877

    申请日：2005-09-30

    申请人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

    发明人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

    IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L27/115 ,  H01L21/76838 ,  H01L27/11521 ,  H01L27/11568

    摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).

    摘要翻译： 半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。 沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。 每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。 因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。 根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。 因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

    Memory element for a semiconductor memory device
    29.
    发明授权
    Memory element for a semiconductor memory device 失效
    用于半导体存储器件的存储元件

    公开(公告)号：US06724038B2

    公开(公告)日：2004-04-20

    申请号：US10223955

    申请日：2002-08-20

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： H01L29792

    CPC分类号： G11C11/5671 ,  G11C11/56 ,  H01L29/7887

    摘要： A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.

    摘要翻译： 存储元件包括彼此隔离的多个材料区域，以在隔离区域中形成具有改变的电和/或磁特性的至少一个区域，该区域具有或形成自由电荷载体。 信息单元可以相应地通过对在区域中提供的线路设备施加电势来影响材料区域而被写入，删除和/或读取。

    Evaluation circuit and evaluation method for the assessment of memory cell states
    30.
    发明申请
    Evaluation circuit and evaluation method for the assessment of memory cell states 失效
    用于评估存储单元状态的评估电路和评估方法

    公开(公告)号：US20070086241A1

    公开(公告)日：2007-04-19

    申请号：US11543306

    申请日：2006-10-04

    申请人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    发明人： Thomas Kern ,  Thomas Mikolajick ,  Jan-Malte Schley

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C27/005

    摘要： An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.

    摘要翻译： 电子电路装置包括设置用于存储至少两个模拟电量的存储单元。 第一评估电路耦合到存储单元并且被设置成使得其评估至少两个模拟电量并提供第一评估结果。 第二评估电路耦合到存储单元并且被设置成使得其以预定阈值评估至少两个模拟电量中的至少一个并提供第二评估结果。