公开(公告)号：US20110256688A1

公开(公告)日：2011-10-20

申请号：US13156970

申请日：2011-06-09

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/76

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

公开(公告)号：US07351642B2

公开(公告)日：2008-04-01

申请号：US11036536

申请日：2005-01-14

申请人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

发明人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

IPC分类号： H01L21/76

CPC分类号： H01L21/31055

摘要： A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.

摘要翻译： 一种用于补偿晶片上的径向不均匀性的方法和方法，包括以下步骤：在CMP工艺之后使膜周围的旋转基座的轴线上的膜的旋转厚度不均匀性居中; 将喷嘴定位在旋转处理单元中以沿着晶片的半径引导蚀刻溶液; 从喷嘴调节蚀刻溶液的流动; 调整旋转基座的旋转速度以控制蚀刻溶液的停留时间; 并协调旋转基座的旋转速度，蚀刻溶液的流动和喷嘴的定位，以最大限度地去除材料。 该方法可用于补偿STI氧化物的碗形不均匀性。 这些非均匀性在CMP过程之后得到补偿和解决。

公开(公告)号：US06649424B2

公开(公告)日：2003-11-18

申请号：US10154340

申请日：2002-05-23

申请人： Manfred Mört ,  Walter Hartner ,  Volker Weinrich ,  Günther Schindler

发明人： Manfred Mört ,  Walter Hartner ,  Volker Weinrich ,  Günther Schindler

IPC分类号： H01L2100

CPC分类号： H01L28/55 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02285 ,  H01L21/31691

摘要： A method of fabricating semiconductor circuits having integrated capacitors that have a dielectric or a ferroelectric material between electrodes. The materials are subjected to heat treatment at high temperatures in an oxygen atmosphere for the purpose of crystallization. The dielectric or ferroelectric is heated separately from the semiconductor substrate, is comminuted into small particles and only afterward applied in this form to the semiconductor substrate. This makes it possible to integrate substances with arbitrarily high crystallization temperature without damaging the integrated semiconductor circuit, since the semiconductor substrate itself does not have to be heated. Diffusion barriers for oxygen are unnecessary. Previous limitations on the capacitor capacitance are obviated owing to the free choice of dielectric or ferroelectric made possible, and the packing density of the capacitors is increased.

公开(公告)号：US06495415B2

公开(公告)日：2002-12-17

申请号：US10027532

申请日：2001-12-26

申请人： Walter Hartner ,  Igor Kasko ,  Volker Weinrich ,  Frank Hintermaier ,  Günther Schindler ,  Hermann Wendt

发明人： Walter Hartner ,  Igor Kasko ,  Volker Weinrich ,  Frank Hintermaier ,  Günther Schindler ,  Hermann Wendt

IPC分类号： H01L218242

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L21/76838 ,  H01L27/10852 ,  H01L28/60

摘要： A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.

公开(公告)号：US06316802B1

公开(公告)日：2001-11-13

申请号：US09282091

申请日：1999-03-30

申请人： Günther Schindler ,  Walter Hartner ,  Frank Hintermaier ,  Carlos Mazure-Espejo ,  Rainer Bruchhaus ,  Wolfgang Hönlein ,  Manfred Engelhardt

发明人： Günther Schindler ,  Walter Hartner ,  Frank Hintermaier ,  Carlos Mazure-Espejo ,  Rainer Bruchhaus ,  Wolfgang Hönlein ,  Manfred Engelhardt

IPC分类号： H01L27108

CPC分类号： H01L27/11502

摘要： The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

摘要翻译： 集成半导体存储器配置具有集成了选择晶体管和存储电容器的半导体本体。 存储电容器具有在两个电极之间配置的电介质层。 至少上电极以分层的方式构成，铂层位于电介质层上，而较厚的贱金属层位于铂层之上。

公开(公告)号：US6136659A

公开(公告)日：2000-10-24

申请号：US47850

申请日：1998-03-25

申请人： Gunther Schindler ,  Walter Hartner ,  Volker Weinrich ,  Carlos Mazure-Espejo

发明人： Gunther Schindler ,  Walter Hartner ,  Volker Weinrich ,  Carlos Mazure-Espejo

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L21/20

CPC分类号： H01L28/65 ,  H01L21/32137

摘要： A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

摘要翻译： 由铂金属形成的电容器电极的制造方法包括在具有用于电容器电极的含硅表面的基板上制造导电电极体。 铂在整个表面上沉积，铂在电极体外部的温度阶段被硅化，除去铂硅化物。 本发明的优点是避免金属铂的蚀刻工艺。

公开(公告)号：US06051485A

公开(公告)日：2000-04-18

申请号：US66245

申请日：1998-04-24

申请人： Gunther Schindler ,  Walter Hartner ,  Dana Pitzer

发明人： Gunther Schindler ,  Walter Hartner ,  Dana Pitzer

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/60

摘要： A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at which the platinum-metal structure or pattern is to be produced; etching the silicon oxide layer so that the substrate surface area exposed by the opening formed in the mask is larger than the opening in the mask; applying a platinum-metal layer to the mask and the exposed substrate surface area; and removing the silicon oxide layer in an etching process, so that the platinum metal present on the mask is removed simultaneously therewith, and the platinum metal present on the substrate surface forms the platinum-metal pattern or structure.

摘要翻译： 一种在基板上制造铂金属结构或图案的方法，包括以下步骤：向基板施加氧化硅层; 在形成有铂金属结构或图案的位置处形成有开口的氧化硅层上施加掩模; 蚀刻氧化硅层，使得由形成在掩模中的开口露出的衬底表面积大于掩模中的开口; 将铂金层施加到掩模和暴露的基底表面区域; 并且在蚀刻工艺中除去氧化硅层，使得存在于掩模上的铂金属与其同时被除去，存在于衬底表面上的铂金属形成铂金属图案或结构。

公开(公告)号：US20140035154A1

公开(公告)日：2014-02-06

申请号：US13564922

申请日：2012-08-02

申请人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

发明人： Ottmar Geitner ,  Walter Hartner ,  Maciej Wojnowski ,  Ulrich Wachter ,  Michael Bauer ,  Andreas Stueckjuergen

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L24/96 ,  H01L23/3128 ,  H01L23/49855 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24051 ,  H01L2224/32245 ,  H01L2224/73151 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/142 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/13 ,  H01L2224/21 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.

摘要翻译： 提供了芯片封装，芯片封装包括：芯片，包括形成在芯片正面上的至少一个接触焊盘; 至少部分地围绕所述芯片并且覆盖所述至少一个接触垫的封装材料; 以及通过所述封装材料形成的至少一个电互连，其中所述至少一个电互连构造成将所述至少一个接触焊盘从所述芯片前侧的芯片封装第一侧电重定向到形成在所述芯片前侧上的至少一个焊料结构 芯片封装第二面在芯片背面。

公开(公告)号：US07468307B2

公开(公告)日：2008-12-23

申请号：US11476497

申请日：2006-06-28

申请人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/76

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

摘要翻译： 半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入 层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。 可以在隔离沟槽内形成与半导体衬底的接触。

公开(公告)号：US20070018195A1

公开(公告)日：2007-01-25

申请号：US11476497

申请日：2006-06-28

申请人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Walter Hartner ,  Andreas Meiser ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L29/74

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

摘要翻译： 半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入 层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。 可以在隔离沟槽内形成与半导体衬底的接触。