Process for making bit selectable devices having elements made with nanotubes
    21.
    发明授权
    Process for making bit selectable devices having elements made with nanotubes 有权
    用于制造具有由纳米管制成的元件的位选择器件的工艺

    公开(公告)号:US07045421B2

    公开(公告)日:2006-05-16

    申请号:US10824706

    申请日:2004-04-15

    IPC分类号: H01L21/00

    摘要: A method is used to make a bit selectable device having nanotube memory elements. A structure having at least two transistors is provided, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel. A trench is formed between one of the source and drain of a first transistor and one of the source and drain of a second transistor. An electrical communication path is formed in the trench between one of the source and drain of a first transistor and one of the source and drain of a second transistor. A defined pattern of nanotube fabric is provided over at least a horizontal portion of the structure and extending into the trench. An electrode is provided in the trench. A pattern of nanotube fabric is suspended so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a first transistor and one of the source and drain of a second transistor.

    摘要翻译: 一种方法用于制造具有纳米管存储元件的位选择器件。 提供了具有至少两个晶体管的结构,每个具有漏极和源极之间具有限定的沟道区域,每个晶体管还包括位于所述沟道上的栅极。 在第一晶体管的源极和漏极之一以及第二晶体管的源极和漏极之一之间形成沟槽。 在第一晶体管的源极和漏极之一以及第二晶体管的源极和漏极中的一个之间的沟槽中形成电连通路径。 在结构的至少一个水平部分上提供限定的纳米管织物图案并且延伸到沟槽中。 在沟槽中设置电极。 纳米管织物的图案被悬浮,使得至少一部分垂直悬挂在与沟槽的垂直壁隔开的位置上,并且被定位成使得垂直悬挂的限定图案的纳米管织物可机电偏转成与排水管之一电连通 第一晶体管的源极和第二晶体管的源极和漏极之一。

    Process for making byte erasable devices having elements made with nanotubes
    22.
    发明授权
    Process for making byte erasable devices having elements made with nanotubes 失效
    用于制造具有由纳米管制成的元件的字节可擦除器件的过程

    公开(公告)号:US06995046B2

    公开(公告)日:2006-02-07

    申请号:US10824678

    申请日:2004-04-15

    IPC分类号: H01L21/335

    摘要: A method of making byte erasable devices having elements made with nanotubes. Under one aspect of the invention, a device is made having nanotube memory elements. A structure is provided having a plurality of transistors, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel. For a predefined set of transistors, a corresponding trench is formed between gates of adjacent transistors. For each trench, a defined pattern of nanotube fabric is provided over at least a horizontal portion of the structure and extending into the trench. An electrode is provided in each trench. Each defined pattern of nanotube fabric is suspended so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a transistor. An electrical communication path is provided electrically connecting each electrode so that all electrodes may electro-statically attract a corresponding defined pattern of nanotube fabric away from a transistor and toward the electrode.

    摘要翻译: 一种制造具有由纳米管制成的元件的字节可擦除器件的方法。 在本发明的一个方面,制造具有纳米管存储元件的装置。 提供了具有多个晶体管的结构,每个具有漏极和源极之间的沟道区域,每个晶体管还包括位于所述沟道上的栅极。 对于预定义的一组晶体管,在相邻晶体管的栅极之间形成相应的沟槽。 对于每个沟槽,在结构的至少水平部分上提供限定的纳米管织物图案并且延伸到沟槽中。 在每个沟槽中设置电极。 每个限定的纳米管织物图案被悬挂,使得至少一部分垂直悬挂在与沟槽的垂直壁隔开的关系中,并且定位成使得垂直悬挂的限定图案的纳米管织物可机电偏转成与漏斗之一电连通 和晶体管的源极。 电气连接路径被电连接每个电极,使得所有电极可以静电吸引相应的限定图案的纳米管织物远离晶体管并朝向电极。

    Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
    24.
    发明授权
    Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same 有权
    非挥发性纳米管二极管和非易失性纳米管块及使用其的系统及其制造方法

    公开(公告)号:US07782650B2

    公开(公告)日:2010-08-24

    申请号:US11835845

    申请日:2007-08-08

    IPC分类号: G11C11/00

    摘要: Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.

    摘要翻译: 在一个方面,存储器阵列包括字线; 位线 记忆细胞; 和存储器操作电路。 每个存储器单元响应于字线和位线上的电刺激,并且包括:具有第一和第二端子的二端非易失性纳米管开关器件,半导体二极管元件和能够具有多个电阻状态的纳米管织物制品 。 半导体二极管和纳米管制品分别与第一和第二端子电连接,并且与第一和第二端子电连接,它们分别耦合到字线位线。 操作电路通过激活位和/或字线来选择单元,检测所选择的存储单元的纳米管织物的电阻状态,并调整施加到单元的电刺激以可控制地引起纳米管织物制品中选定的电阻状态。 选择的电阻状态对应于存储单元的信息状态。

    Nanotube-based switching elements with multiple controls and logic circuits having said elements
    30.
    发明授权
    Nanotube-based switching elements with multiple controls and logic circuits having said elements 有权
    具有多个控制器和具有所述元件的逻辑电路的基于纳米管的开关元件

    公开(公告)号:US07710157B2

    公开(公告)日:2010-05-04

    申请号:US12246013

    申请日:2008-10-06

    IPC分类号: H03K19/20

    摘要: Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel along the nanotube channel element. At least one nanotube switching element non-volatilely retains an informational state and at least one nanotube switching elements volatilely retains an informational state. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. Dual rail cascode logic circuits may also be constructed from the nanotube switching elements.

    摘要翻译: 包括具有多个控制的基于纳米管的开关元件的布尔逻辑电路。 布尔逻辑电路包括输入和输出端子以及电气设置在所述至少一个输入端子和所述输出端子之间的纳米管开关元件网络。 每个开关元件包括输入节点,输出节点和具有至少一个导电纳米管的纳米管通道元件。 相对于纳米管通道元件设置控制结构,以可控地形成和取消沿着纳米管通道元件的导电通道。 至少一个纳米管开关元件不挥发地保持信息状态,并且至少一个纳米管开关元件挥发性地保持信息状态。 纳米管切换元件的网络在所述至少一个输入端上实现布尔信号的布尔函数变换。 双轨共源共栅逻辑电路也可以由纳米管开关元件构成。