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    Contacts and vias of a semiconductor device formed by a hard mask and double exposure
    21.
    发明授权
    Contacts and vias of a semiconductor device formed by a hard mask and double exposure 有权
    通过硬掩模和双重曝光形成的半导体器件的触点和通孔

    公开(公告)号：US08318598B2

    公开(公告)日：2012-11-27

    申请号：US12537321

    申请日：2009-08-07

    申请人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    发明人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

    摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

    摘要翻译： 可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸 接触元件。 因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。

    Dual Cavity Etch for Embedded Stressor Regions
    22.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。

    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE
    27.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE 有权
    用于不同阈值电压器件的高K栅极堆栈中的工作功能调整

    公开(公告)号：US20110127616A1

    公开(公告)日：2011-06-02

    申请号：US12905501

    申请日：2010-10-15

    申请人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/28176 ,  H01L21/823857 ,  H01L29/517

    摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.

    摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。 以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。

    MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATION USING AN OXYGEN PLASMA
    28.
    发明申请
    MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATION USING AN OXYGEN PLASMA 有权
    通过使用氧气等离子体进行钝化保持高K栅格堆叠的完整性

    公开(公告)号：US20110049585A1

    公开(公告)日：2011-03-03

    申请号：US12848644

    申请日：2010-08-02

    申请人： Sven Beyer ,  Rick Carter ,  Andreas Hellmich ,  Berthold Reimer

    发明人： Sven Beyer ,  Rick Carter ,  Andreas Hellmich ,  Berthold Reimer

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28

    CPC分类号： H01L21/28247 ,  H01L21/0206 ,  H01L21/02244 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

    摘要： In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.

    摘要翻译： 在半导体器件中，通过在形成薄的氮化硅基材料之后将材料暴露于氧等离子体，可以提高氮化钛材料的完整性。 氧等离子体可能导致任何微小表面部分的附加钝化，这些微小表面部分可能不被氮化硅基材料适当地覆盖。 因此，可以在附加钝化之后进行有效的清洁配方，例如基于SPM的清洁方法，而不会导致氮化钛材料的不适当的材料损失。 以这种方式，可以在有效的清洁过程的基础上形成具有非常薄的保护衬垫材料的复杂的高k金属栅极堆叠，而不会在早期制造阶段中过度地造成显着的产量损失。

    ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING
    29.
    发明申请
    ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING 有权
    通过在半导体加工过程中提供化学氧化物层，在含氮层包括层堆叠的过程中增强蚀刻阻挡能力

    公开(公告)号：US20100304542A1

    公开(公告)日：2010-12-02

    申请号：US12785849

    申请日：2010-05-24

    申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/513 ,  H01L29/66583 ,  H01L29/7833

    摘要： A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

    摘要翻译： 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成，其可以基于化学驱动的氧化工艺形成。 由于厚度减小，可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀，从而不会过度影响进一步的加工，例如关于形成嵌入式应变诱导半导体合金， 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。