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公开(公告)号：US07159134B2
公开(公告)日：2007-01-02
申请号：US10230534
申请日：2002-08-29
申请人： Joern Soerensen , Hitesh Anand , Michael S. Allen
发明人： Joern Soerensen , Hitesh Anand , Michael S. Allen
CPC分类号： G06F11/3636 , G06F1/04 , G06F1/08 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3836 , G06F9/3851 , G06F9/3869 , G06F9/4843 , G06F12/0842 , G06F12/0859 , G06F13/28 , G06F13/385 , G06F2213/3814 , H03L7/0802 , H03L7/095 , H03L7/183 , H04W88/06 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/171 , Y02D10/172 , Y02D10/24 , Y02D50/20 , Y02D70/1222 , Y02D70/124 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y10S331/02
摘要： A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.
摘要翻译： 提供了一种数字基带处理器，其接收由系统振荡器产生的系统时钟，并从系统时钟产生多个时钟信号。 数字基带处理器包括用于执行数字信号处理器指令的数字信号处理器，用于执行微控制器指令的微控制器以及可能需要多个时钟信号中的一个用于操作的其它模块。 数字基带处理器还包括一个电源管理电路，当诸如数字信号处理器和微控制器的模块不需要从系统振荡器导出的时钟信号时，该电源管理电路可能会关闭系统振荡器。 当这些模块不需要时钟信号而不关闭系统振荡器时，电源管理电路可以关闭时钟信号到模块。
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公开(公告)号：US06988167B2
公开(公告)日：2006-01-17
申请号：US09779209
申请日：2001-02-08
申请人： Michael S. Allen , Moinul I. Syed
发明人： Michael S. Allen , Moinul I. Syed
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g., as compared to a multi-port cache), and to alleviate the difficulty associated with addressing the non-contiguous internal address map of the cache. By employing a DMA controller having flexible address generation and transfer control capabilities, data can be transferred from an atypical memory-mapped entity (e.g., a FIFO buffer of a peripheral) directly to the cache.
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23.发明授权
公开(公告)号：US5835946A
公开(公告)日：1998-11-10
申请号：US634907
申请日：1996-04-18
申请人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
发明人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
CPC分类号： G06F9/3004 , G06F12/0875 , G06F9/30087 , G06F12/0897
摘要： The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.
摘要翻译： 本发明提供了一种用于在超标量处理器中有效执行负载储备（LARX）和存储条件（STCX）指令的系统和方法。 公开了一种用于在超标量处理器中有效提供LARX指令的系统。 该系统包括用于接收LARX指令的数据高速缓存（Dcache）。 数据高速缓存还包括用于设置和重置负载保留指令的验证的解码器装置，用于接收地址信息并用于提供数据的内部高速缓存。 该系统还包括用于接收LARX指令的寄存器装置和用于基于地址信息提供物理地址的控制器装置。 当在内部数据高速缓存上存在命中时，系统提供在LARX指令的一个周期内完成的验证。
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24.发明授权Priority arbitration protocol with two resource requester classes and system therefor 失效具有两个资源请求者类和系统的优先仲裁协议
公开(公告)号：US5649206A
公开(公告)日：1997-07-15
申请号：US482955
申请日：1995-06-15
申请人： Michael S. Allen
发明人： Michael S. Allen
IPC分类号： G06F13/364 , G06F13/14
CPC分类号： G06F13/364
摘要： An arbitration protocol (68) comprises the steps of receiving a first (70) and a second (74) plurality of resource request signals, and either, granting the shared resource to a selected one of a first plurality of resource users (72) or granting the shared resource to a selected one of a second plurality of resource users (76). A differing one of each of a first plurality of resource users and of each of a second plurality of resource users generates a differing one of the first plurality of resource request signals and a differing one of the second plurality of resource request signals, respectively. Each one of the first and the second plurality of resource request signals corresponds to a first logic state if a particular one of the first or second plurality of resource users requests use of a shared resource. The shared resource is granted to a selected one of the first plurality of resource users according to a first arbitration protocol if at least one of the first plurality of resource request signals corresponds to the first logic state. The shared resource is granted to a selected one of the second plurality of resource users according to a second arbitration protocol if none of the first plurality of resource request signals corresponds to the first logic state and at least one of the second plurality of resource request signals corresponds to the first logic state.
摘要翻译： 仲裁协议（68）包括以下步骤：接收第一（70）和第二（74）个多个资源请求信号，以及将所述共享资源授予所述第一多个资源用户（72）或 将所述共享资源授权给第二多个资源用户（76）中的所选择的一个。 第一多个资源用户和第二多个资源用户中的每一个资源用户中的每一个的不同的一个分别生成第一多个资源请求信号中的不同的一个和第二多个资源请求信号中的不同的一个。 第一和第二多个资源请求信号中的每一个对应于第一或第二多个资源用户中的特定一个资源请求使用共享资源的第一逻辑状态。 如果第一多个资源请求信号中的至少一个对应于第一逻辑状态，则根据第一仲裁协议将共享资源授予第一多个资源用户中的所选择的一个。 如果没有第一多个资源请求信号对应于第一逻辑状态和第二多个资源请求信号中的至少一个，则根据第二仲裁协议将共享资源授予第二多个资源用户中的所选择的一个资源用户 对应于第一个逻辑状态。
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公开(公告)号：US5884225A
公开(公告)日：1999-03-16
申请号：US795106
申请日：1997-02-06
CPC分类号： A01G7/00
摘要： A system and a method for providing farmers/producers with crop characteristic predictions for standing crops located in fields includes a central database for storing field and crop information for the crops. A weather data processor receives raw weather data from either or both of (1) a weather data service with collected weather data from a plurality of weather stations; and (2) one or more site-specific weather stations associated with a particular field whose information is in the database. The raw weather data are processed to obtain field weather parameters for entry into a crop characteristic prediction equation, and the parameters are stored in the central database. With a user interface, a crop whose information is stored in the central database is selected. A computer calculates a crop characteristic prediction for the selected field based on the crop and field information stored in the central database, including the field weather parameters in the database, and the crop characteristic prediction formula. The producer uses the prediction to determine time of harvest. In one embodiment, the crops are alfalfa crops and the crop characteristic is neutral detergent fiber content.
摘要翻译： 为农民/生产者提供位于田间的常见作物的作物特征预测的系统和方法包括用于存储作物的田间和作物信息的中心数据库。 天气数据处理器从（1）天气数据服务中的一个或两个接收原始天气数据，并从多个气象站收集天气数据; 和（2）与信息在数据库中的特定领域相关联的一个或多个站点特定的气象站。 处理原始天气数据以获得用于进入作物特征预测方程的场天气参数，并且将参数存储在中央数据库中。 使用用户界面，选择其信息存储在中央数据库中的裁剪。 计算机基于存储在中央数据库中的作物和场信息（包括数据库中的田间天气参数）和作物特征预测公式来计算所选场的作物特征预测。 生产者使用预测来确定收获时间。 在一个实施方案中，作物是苜蓿作物，作物特征是中性洗涤剂纤维含量。
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26.发明授权
公开(公告)号：US5608878A
公开(公告)日：1997-03-04
申请号：US316980
申请日：1994-10-03
CPC分类号： G06F12/0831
摘要： A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.
摘要翻译： 多处理系统利用具有两个响应窗口的总线协议。 第一响应窗口处于来自总线请求和/或地址传输的固定延迟时间，而用于一致性报告的第二响应窗口在总线请求和地址之后被放置成可配置数量的时钟周期，以允许更长时间 访问或窥探时间，以执行其他总线设备内的缓存目录查找。 第一个响应窗口报告错误或流量控制和错误状态。 此外，已经描述了以灵活和高性能的方式报告响应信息的方法。
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公开(公告)号：US5553629A
公开(公告)日：1996-09-10
申请号：US31257
申请日：1993-03-11
CPC分类号： A61B18/22 , A61B2017/00141 , A61B2017/00154 , A61B2017/00172 , A61B2090/502 , A61F17/00
摘要： A fiber optic cable has one end directly coupled to a semiconductor IR generating laser diode array and the other end is used to direct IR radiation at a soldier's wound for surgical purposes. The beam may also be used to illuminate a dark scene to detect the presence of a present threat such as a sniper. The components are conveniently carried by the medically trained person in his belt pack so as not to interfere with his freedom of movement. Disposable IR applicator tips may also be provided to be attached to the IR exit portion of the fiber optic cable.
摘要翻译： 光纤电缆的一端直接耦合到半导体IR产生激光二极管阵列，另一端用于引导士兵伤口处的IR辐射用于外科用途。 光束也可用于照亮黑暗场景以检测当前威胁的存在，例如狙击手。 这些部件由医疗训练有素的人携带在皮带包中，以免干扰他的运动自由。 还可以提供一次性IR施加器尖端以附接到光纤电缆的IR出口部分。
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公开(公告)号：USD349952S
公开(公告)日：1994-08-23
申请号：US3237
申请日：1992-12-31
申请人： Thomas L. Evans , Michael S. Allen
设计人： Thomas L. Evans , Michael S. Allen
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公开(公告)号：US5319190A
公开(公告)日：1994-06-07
申请号：US29844
申请日：1993-03-11
IPC分类号： H04B10/114 , H04B10/116 , H01J40/14
CPC分类号： H04B10/114 , H04B10/116
摘要： A method of providing near simultaneous night vision and communication including directing a narrow voice modulated IR laser beam at a distant receiver/demodulator during communication periods, causing the IR laser beam to diverge substantially during scene viewing periods, other than the data communication periods, for illuminating a darkened scene which includes the laser beam receiver, and viewing the darkened scene with an IR viewing device.
摘要翻译： 提供近似同时的夜视和通信的方法，包括在通信周期期间在远距离的接收机/解调器处引导窄的语音调制的红外激光束，导致IR激光束在除数据通信周期之外的场景观看期间基本上发散， 照亮包含激光束接收器的黑暗场景，并用红外观察装置观看黑暗场景。
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公开(公告)号：US06981122B2
公开(公告)日：2005-12-27
申请号：US10255399
申请日：2002-09-26
申请人： Thomas A. Volpe , Michael S. Allen , Aaron Bauch
发明人： Thomas A. Volpe , Michael S. Allen , Aaron Bauch
CPC分类号： G06F12/0653
摘要： A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.
摘要翻译： 提供了一种用于操作存储器系统的存储器系统和方法。 存储器系统包括一组存储器组，用于从存储器组集合计算每个存储器组中的第一地址的逻辑，以及从计算设备接收传输地址的控制器。 所述控制器包括用于基于所述传输地址和所述存储体的所述第一地址从所述存储体组中选择存储体的逻辑，以及用于基于所述存储体中的第一地址将所述传送地址映射到所述选择的存储体中的目标地址 所选择的存储体。 结果，存储器组的集合具有连续的存储器空间。
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