公开(公告)号：US20070040216A1

公开(公告)日：2007-02-22

申请号：US11505337

申请日：2006-08-17

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L29/76

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US07138698B2

公开(公告)日：2006-11-21

申请号：US11007254

申请日：2004-12-09

申请人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

发明人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

IPC分类号： H01L23/58

CPC分类号： H02M3/158 ,  H01L27/0922 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2924/0002 ,  H02M1/08 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

公开(公告)号：US07034357B2

公开(公告)日：2006-04-25

申请号：US10724825

申请日：2003-12-02

申请人： Tomoko Matsudai ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Akio Nakagawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/1095 ,  H01L29/7397

摘要： An insulated gate semiconductor device includes a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the second base layer a channel electrically connecting between the source layer and the first base layer, wherein the voltage transiently applied to the device is larger than the static breakdown voltage between the source and the drain when a rated current is turned off under a condition, in which condition the device is connected to an inductance load without using a protective circuit.

摘要翻译： 绝缘栅半导体器件包括第一导电类型的第一基极层; 形成在所述第一基底层的第一表面上的第二导电类型的第二基底层; 选择性地形成在所述第二基底层的表面区域中的所述第一导电型的源极层; 所述第二导电类型的漏极层形成在所述第一基底层的与所述第一表面相对的第二表面上; 以及与所述源极层，所述第一基极层和所述第二基极层绝缘的栅电极，并且在所述第二基极层中形成电连接所述源极层与所述第一基极层之间的沟道，其中瞬时施加到所述器件的电压较大 比在额定电流在条件下关闭时在源极和漏极之间的静态击穿电压，在该条件下，器件在不使用保护电路的情况下连接到电感负载。

公开(公告)号：US06620653B2

公开(公告)日：2003-09-16

申请号：US09961361

申请日：2001-09-25

申请人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

IPC分类号： H01L21332

CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66333

摘要： A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

摘要翻译： 在半导体衬底的一个表面的一侧上形成负极缓冲层和正极集电极层。 正极集电极层被设定为具有低剂量并且设置得较浅，从而实现了低注入效率的发射极结构。 功率器件的击穿电压由漂移层的厚度控制。 在半导体基板的另一个表面的一侧上形成正基极层，负极发射极层和正极基极接触层。 负极低电阻层降低结FET影响。 发射极电极与负极发射极层和正极基极接触层接触。 集电极与正极集电极层接触。 栅极电极形成在阳极基极层的表面部分上的沟道区域上方的栅极绝缘膜上。

公开(公告)号：US5920087A

公开(公告)日：1999-07-06

申请号：US970103

申请日：1997-11-13

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

摘要翻译： 子栅电极配置成通过栅极绝缘膜与介于第一n型源极层和n型漂移层之间的第一p型基极层的表面和 第二p型基极层，其介于第二n型源极层和n型漂移层之间并且面向第一p型基极层。 主栅极布置成通过栅极绝缘膜面对介于第二n型源极层和n型漂移层之间的第二p型基极层的表面，并且不面向第一p 型基层。 构造三个n型MOSFET，使得在第一p型基极层中形成一个n型沟道，并且在第二p型基极层中形成两个n型沟道。 要形成三个通道，从而有效地扩大通道宽度，增加电流密度。 第二p型基层在漂移方向上的长度为10μm以下。

公开(公告)号：US5796125A

公开(公告)日：1998-08-18

申请号：US528570

申请日：1995-09-15

申请人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76 ,  H01L29/94 ,  H01L31/111

CPC分类号： H01L29/0696 ,  H01L29/7394 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7824 ,  H01L29/4238

摘要： A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.

摘要翻译： 高耐压半导体器件。 该器件包括半导体衬底，形成在半导体衬底上的绝缘膜，形成在绝缘膜上的有源区，形成在有源区的表面部分中的漏极和基极区以及形成在有源区的表面部分中的源极区 基地区。 第一和第二栅极绝缘膜形成在穿过基极区域的第一和第二沟槽的内表面上，以便与源极区域接触并到达有源区域，第一和第二电极被埋在第一和第二沟槽中。 由栅极绝缘膜，栅极电极，源极区域，基极区域和有源区域构成的MOS结构中形成有两个以上的沟道区域。

公开(公告)号：US5751022A

公开(公告)日：1998-05-12

申请号：US806153

申请日：1997-02-25

申请人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/749 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7455

摘要： A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

摘要翻译： 公开了具有耦合到半导体开关器件和半导体整流器的晶闸管区域的半导体器件。 在关断操作期间，从晶闸管区域的p型基极区域通过半导体整流器和晶闸管的阴极排出孔。 在导通期间，电子通过半导体开关器件从阴极电极提供给晶闸管的n型发射极区域。

公开(公告)号：US5731603A

公开(公告)日：1998-03-24

申请号：US701500

申请日：1996-08-22

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

公开(公告)号：US5708287A

公开(公告)日：1998-01-13

申请号：US564449

申请日：1995-11-29

申请人： Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Tomoko Matsudai

发明人： Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Tomoko Matsudai

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： An n.sup.- -type silicon active layer having a thickness of 6 .mu.m or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the active layer. The two devices are insulated and isolated from each other through a trench. The bipolar transistor has an n-type well layer formed in the surface of the active layer. A p-type well layer is formed in the surface of the n-type well layer. The thickness of the n-type well layer under the p-type well layer is set to be 1 .mu.m or more. A first n.sup.+ -type diffusion layer is formed in the surface of the n-type well layer. A p.sup.+ -type diffusion layer and a second n.sup.+ -type diffusion layer are formed in the surface of the p-type well layer. The n-type well layer and the first n.sup.+ -type diffusion layer serve as a collector region. The p-type well layer and the p.sup.+ -type diffusion layer serve as a base region. The second n.sup.+ -type diffusion layer serves as an emitter region.

摘要翻译： 通过氧化硅膜在硅衬底上形成厚度为6μm以下的n型硅有源层。 在有源层中形成具有低耐压的npn双极晶体管和具有高耐压的IGBT。 两个器件通过沟槽彼此绝缘和隔离。 双极晶体管在有源层的表面形成有n型阱层。 p型阱层形成于n型阱层的表面。 p型阱层下面的n型阱层的厚度设定为1μm以上。 在n型阱层的表面形成第一n +型扩散层。 在p型阱层的表面形成p +型扩散层和第n +型扩散层。 n型阱层和第一n +型扩散层用作集电极区域。 p型阱层和p +型扩散层用作基极区域。 第二n +型扩散层用作发射极区域。

公开(公告)号：US08981473B2

公开(公告)日：2015-03-17

申请号：US13410739

申请日：2012-03-02

申请人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。