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    Semiconductor device and method of manufacturing the same
    1.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06620653B2

    公开(公告)日：2003-09-16

    申请号：US09961361

    申请日：2001-09-25

    申请人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

    IPC分类号： H01L21332

    CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66333

    摘要： A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

    摘要翻译： 在半导体衬底的一个表面的一侧上形成负极缓冲层和正极集电极层。 正极集电极层被设定为具有低剂量并且设置得较浅，从而实现了低注入效率的发射极结构。 功率器件的击穿电压由漂移层的厚度控制。 在半导体基板的另一个表面的一侧上形成正基极层，负极发射极层和正极基极接触层。 负极低电阻层降低结FET影响。 发射极电极与负极发射极层和正极基极接触层接触。 集电极与正极集电极层接触。 栅极电极形成在阳极基极层的表面部分上的沟道区域上方的栅极绝缘膜上。

    Punch through type power device
    2.
    发明授权
    Punch through type power device 有权
    打孔式电源设备

    公开(公告)号：US06686613B2

    公开(公告)日：2004-02-03

    申请号：US10383515

    申请日：2003-03-10

    申请人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

    IPC分类号： H01L29423

    CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66333

    摘要： A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

    摘要翻译： 在半导体衬底的一个表面的一侧上形成负极缓冲层和正极集电极层。 正极集电极层被设定为具有低剂量并且设置得较浅，从而实现了低注入效率的发射极结构。 功率器件的击穿电压由漂移层的厚度控制。 在半导体基板的另一个表面的一侧上形成正基极层，负极发射极层和正极基极接触层。 负极低电阻层降低结FET影响。 发射极电极与负极发射极层和正极基极接触层接触。 集电极与正极集电极层接触。 栅极电极形成在阳极基极层的表面部分上的沟道区域上方的栅极绝缘膜上。

    Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate
    3.
    发明授权
    Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate 失效
    在单个基板上提供具有水平MOSFET和肖特基势垒二极管的半导体器件

    公开(公告)号：US07432579B2

    公开(公告)日：2008-10-07

    申请号：US10959201

    申请日：2004-10-07

    申请人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

    IPC分类号： H01L29/47 ,  H01L29/872

    CPC分类号： H01L27/0727

    摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.

    摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层， 所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和 栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。 肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一 和第二漏区。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06914294B2

    公开(公告)日：2005-07-05

    申请号：US10438069

    申请日：2003-05-15

    申请人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

    发明人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L31/113

    CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7801

    摘要： A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.

    摘要翻译： 半导体器件包括具有主表面的半导体衬底; 设置在所述半导体衬底的主表面上的第一导电类型的半导体层; 设置在所述半导体层和所述半导体衬底之间的第一导电类型的第一掩埋层; 所述第一导电类型的第一连接区域设置在所述第一掩埋层周围，所述第一连接区域从所述半导体层的表面延伸到所述第一掩埋层; 设置在所述第一掩埋层的所述半导体层的表面区域中的开关元件; 以及设置在所述半导体层的表面区域中的低击穿电压元件，所述低击穿电压元件比所述开关元件更靠近所述第一连接区域，并且具有比所述开关元件的击穿电压低的击穿电压。

    Method of manufacturing vertical power device
    5.
    发明授权
    Method of manufacturing vertical power device 失效
    垂直功率器件的制造方法

    公开(公告)号：US5985708A

    公开(公告)日：1999-11-16

    申请号：US816596

    申请日：1997-03-13

    申请人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

    发明人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

    IPC分类号： H01L27/12 ,  H01L29/73 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8249

    CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78639 ,  H01L29/78645 ,  H01L29/78687

    摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

    摘要翻译： 一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层， 所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极， 以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层，和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

    Semiconductor device
    7.
    再颁专利
    Semiconductor device 失效
    半导体器件

    公开(公告)号：USRE38907E1

    公开(公告)日：2005-12-06

    申请号：US10452203

    申请日：2003-06-02

    申请人： Tomoko Matsudai ,  Tsutomu Kojima ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Tsutomu Kojima ,  Akio Nakagawa

    IPC分类号： H03K5/22 ,  H03K5/24 ,  H03K17/082 ,  H03K17/10 ,  H03K17/14

    CPC分类号： H03K17/102 ,  H03K5/2481 ,  H03K17/0828 ,  H03K17/145

    摘要： The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.

    摘要翻译： 比较器电路的差分放大器包括用于接收输入信号的第一和第二n型MOSFET，电流镜电路的第一和第二p型MOSFET以及电流源电路的第三n型MOSFET。 输出级包括用于传输信号的第三p型MOSFET和电流源电路的第四n型MOSFET。 差分放大器还包括分别串联连接到第一和第二n型MOSFET的第五和第六n型MOSFET。 输出级还包括与第四n型MOSFET串联连接的第七n型MOSFET。 第五，第六和第七n型MOSFET的栅极连接到电压偏置电路。 第五，第六和第七n型MOSFET抑制由于第一，第二和第四主n型MOSFET的饱和特性不良引起的输出节点的电压变化。

    High voltage semiconductor device having two buffer layer
    8.
    发明授权
    High voltage semiconductor device having two buffer layer 失效
    具有两个缓冲层的高电压半导体器件

    公开(公告)号：US06683343B2

    公开(公告)日：2004-01-27

    申请号：US10084051

    申请日：2002-02-28

    申请人： Tomoko Matsudai ,  Akio Nakagawa

    发明人： Tomoko Matsudai ,  Akio Nakagawa

    IPC分类号： H01L2976

    CPC分类号： H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

    摘要： In an IGBT, an n buffer layer is formed under an n− high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain layer is doped at a low dose, the efficiency of carrier injection can be reduced and a high-speed operation is possible without lifetime control. Since no lifetime control is performed, the on-state voltage can be low. Since the n buffer layer does not immediately stop the extension of the depletion layer during a turn-off period, oscillation of the current and voltage is prevented. The n+ buffer layer maintains a sufficient withstand voltage when a reverse bias is applied.

    摘要翻译： 在IGBT中，n型缓冲层形成在形成有MOS栅极结构的n +高电阻层的下方。 在n缓冲层和p +漏极层之间形成n + +缓冲层。 由于p +漏极层以低剂量掺杂，所以可以降低载流子注入的效率，并且可以在没有寿命的情况下进行高速操作。 由于不进行寿命控制，因此导通电压可以低。 由于n缓冲层在关断期间不会立即停止耗尽层的延伸，所以防止了电流和电压的振荡。 当施加反向偏压时，n + +缓冲层保持足够的耐受电压。