公开(公告)号：US5796125A

公开(公告)日：1998-08-18

申请号：US528570

申请日：1995-09-15

申请人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Mitsuhiko Kitagawa ,  Akio Nakagawa

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76 ,  H01L29/94 ,  H01L31/111

CPC分类号： H01L29/0696 ,  H01L29/7394 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7824 ,  H01L29/4238

摘要： A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.

摘要翻译： 高耐压半导体器件。 该器件包括半导体衬底，形成在半导体衬底上的绝缘膜，形成在绝缘膜上的有源区，形成在有源区的表面部分中的漏极和基极区以及形成在有源区的表面部分中的源极区 基地区。 第一和第二栅极绝缘膜形成在穿过基极区域的第一和第二沟槽的内表面上，以便与源极区域接触并到达有源区域，第一和第二电极被埋在第一和第二沟槽中。 由栅极绝缘膜，栅极电极，源极区域，基极区域和有源区域构成的MOS结构中形成有两个以上的沟道区域。

公开(公告)号：US07432579B2

公开(公告)日：2008-10-07

申请号：US10959201

申请日：2004-10-07

申请人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Kazutoshi Nakamura ,  Akio Nakagawa

IPC分类号： H01L29/47 ,  H01L29/872

CPC分类号： H01L27/0727

摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.

摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层， 所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和 栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。 肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一 和第二漏区。

公开(公告)号：US06914294B2

公开(公告)日：2005-07-05

申请号：US10438069

申请日：2003-05-15

申请人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

发明人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Yusuke Kawaguchi ,  Akio Nakagawa

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7801

摘要： A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.

摘要翻译： 半导体器件包括具有主表面的半导体衬底; 设置在所述半导体衬底的主表面上的第一导电类型的半导体层; 设置在所述半导体层和所述半导体衬底之间的第一导电类型的第一掩埋层; 所述第一导电类型的第一连接区域设置在所述第一掩埋层周围，所述第一连接区域从所述半导体层的表面延伸到所述第一掩埋层; 设置在所述第一掩埋层的所述半导体层的表面区域中的开关元件; 以及设置在所述半导体层的表面区域中的低击穿电压元件，所述低击穿电压元件比所述开关元件更靠近所述第一连接区域，并且具有比所述开关元件的击穿电压低的击穿电压。

公开(公告)号：US5985708A

公开(公告)日：1999-11-16

申请号：US816596

申请日：1997-03-13

申请人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L27/12 ,  H01L29/73 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8249

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78639 ,  H01L29/78645 ,  H01L29/78687

摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

摘要翻译： 一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层， 所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极， 以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层，和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

公开(公告)号：US5343067A

公开(公告)日：1994-08-30

申请号：US829214

申请日：1992-01-31

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

摘要翻译： 一种高耐压半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘层，形成在绝缘层上的高电阻半导体层，形成在高电阻半导体层中的隔离区，形成在高电阻半导体中的元件区 在横向方向上被隔离区域隔离的层，形成在元件区域的中心表面部分中的第一导电类型的第一低电阻区域和形成在元件区域的中心表面部分中的第二导电类型的第二低电阻区域， 元素区域。 元件区域中的杂质的剂量被设定为使得当在第一和第二低电阻区域之间施加电压时，第一低电阻区域和第二低电阻区域之间的元件区域的一部分被完全耗尽。

公开(公告)号：US07579669B2

公开(公告)日：2009-08-25

申请号：US11549297

申请日：2006-10-16

申请人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

发明人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

IPC分类号： H01L27/00

CPC分类号： H02M3/158 ,  H01L27/0922 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2924/0002 ,  H02M1/08 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

摘要翻译： 半导体器件包括高侧开关元件，驱动电路和低侧开关元件。 高侧开关元件形成在第一半导体基板上，其一端具有输入电压的电流通路，电流路径的另一端与电感连接。 驱动电路形成在形成有高侧开关元件的第一半导体基板上，驱动高侧开关元件。 低侧开关元件形成在与第一半导体衬底分离的第二半导体衬底上，并且具有连接到电感的漏极和被提供参考电位的源极。

公开(公告)号：US07138698B2

公开(公告)日：2006-11-21

申请号：US11007254

申请日：2004-12-09

申请人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

发明人： Kazutoshi Nakamura ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita ,  Akio Nakagawa

IPC分类号： H01L23/58

CPC分类号： H02M3/158 ,  H01L27/0922 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2924/0002 ,  H02M1/08 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

公开(公告)号：US07034357B2

公开(公告)日：2006-04-25

申请号：US10724825

申请日：2003-12-02

申请人： Tomoko Matsudai ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Akio Nakagawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/1095 ,  H01L29/7397

摘要： An insulated gate semiconductor device includes a first base layer of a first conduction type; a second base layer of a second conduction type formed on a first surface of the first base layer; a source layer of the first conduction type selectively formed in a surface region of the second base layer; a drain layer of the second conduction type formed on a second surface of the first base layer opposite from said first surface; and a gate electrode insulated from the source layer, the first base layer and the second base layer and forming in the second base layer a channel electrically connecting between the source layer and the first base layer, wherein the voltage transiently applied to the device is larger than the static breakdown voltage between the source and the drain when a rated current is turned off under a condition, in which condition the device is connected to an inductance load without using a protective circuit.

摘要翻译： 绝缘栅半导体器件包括第一导电类型的第一基极层; 形成在所述第一基底层的第一表面上的第二导电类型的第二基底层; 选择性地形成在所述第二基底层的表面区域中的所述第一导电型的源极层; 所述第二导电类型的漏极层形成在所述第一基底层的与所述第一表面相对的第二表面上; 以及与所述源极层，所述第一基极层和所述第二基极层绝缘的栅电极，并且在所述第二基极层中形成电连接所述源极层与所述第一基极层之间的沟道，其中瞬时施加到所述器件的电压较大 比在额定电流在条件下关闭时在源极和漏极之间的静态击穿电压，在该条件下，器件在不使用保护电路的情况下连接到电感负载。

公开(公告)号：US06620653B2

公开(公告)日：2003-09-16

申请号：US09961361

申请日：2001-09-25

申请人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Hidetaka Hattori ,  Akio Nakagawa

IPC分类号： H01L21332

CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66333

摘要： A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

摘要翻译： 在半导体衬底的一个表面的一侧上形成负极缓冲层和正极集电极层。 正极集电极层被设定为具有低剂量并且设置得较浅，从而实现了低注入效率的发射极结构。 功率器件的击穿电压由漂移层的厚度控制。 在半导体基板的另一个表面的一侧上形成正基极层，负极发射极层和正极基极接触层。 负极低电阻层降低结FET影响。 发射极电极与负极发射极层和正极基极接触层接触。 集电极与正极集电极层接触。 栅极电极形成在阳极基极层的表面部分上的沟道区域上方的栅极绝缘膜上。

公开(公告)号：US5920087A

公开(公告)日：1999-07-06

申请号：US970103

申请日：1997-11-13

申请人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/739 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L29/66325 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/7398

摘要： A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

摘要翻译： 子栅电极配置成通过栅极绝缘膜与介于第一n型源极层和n型漂移层之间的第一p型基极层的表面和 第二p型基极层，其介于第二n型源极层和n型漂移层之间并且面向第一p型基极层。 主栅极布置成通过栅极绝缘膜面对介于第二n型源极层和n型漂移层之间的第二p型基极层的表面，并且不面向第一p 型基层。 构造三个n型MOSFET，使得在第一p型基极层中形成一个n型沟道，并且在第二p型基极层中形成两个n型沟道。 要形成三个通道，从而有效地扩大通道宽度，增加电流密度。 第二p型基层在漂移方向上的长度为10μm以下。