公开(公告)号：US09164951B2

公开(公告)日：2015-10-20

申请号：US13637776

申请日：2011-05-24

Applicant: Toshiki Takeuchi ,  Hiroyuki Igura

Inventor： Toshiki Takeuchi ,  Hiroyuki Igura

IPC: G06F15/173

CPC classification number: G06F15/17337

Abstract: The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determines whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.

Abstract translation: 多处理器系统包括一个或多个主处理器和多个子处理器，以及执行控制电路，其执行每个子处理器的执行控制，其中执行控制电路包括用于执行控制处理的执行控制处理器 每个子处理器，用于激活每个子处理器的命令的控制总线输出单元，用于来自每个子处理器的状态通知的状态总线输入单元，确定状态通知是否具有 一个一对一的依赖关系，一个接下来要在操作序列上发出的处理命令，并且要高速处理的状态加速器，当高速处理状态通知时发出相应的处理激活命令 以及状态FIFO控制单元，其通过使用执行控制处理器来处理状态通知。

公开(公告)号：US08989242B2

公开(公告)日：2015-03-24

申请号：US13984792

申请日：2012-02-07

Applicant: Toshiki Takeuchi ,  Hiroyuki Igura

Inventor： Toshiki Takeuchi ,  Hiroyuki Igura

IPC: H04B1/38 ,  H04L1/00 ,  H03M13/09 ,  H03M13/23 ,  H03M13/27 ,  H03M13/00 ,  H03M13/29 ,  H03M13/41

CPC classification number: H04L1/0014 ,  H03M13/09 ,  H03M13/091 ,  H03M13/235 ,  H03M13/2707 ,  H03M13/2732 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/41 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6519 ,  H03M13/6561 ,  H04L1/0043 ,  H04L1/0052 ,  H04L1/0071

Abstract: An encoding/decoding processor includes a coprocessor that is dedicated to encoding and decoding processes, where the coprocessor comprises: a parameter register that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner, and the coprocessor further comprises memory controllers, which include: address generator circuits for outputting the addresses of the storage devices; FIFO circuits for temporarily storing data; and data packing circuits for making up predetermined numbers of bits of data for output.

Abstract translation: 编码/解码处理器包括专用于编码和解码处理的协处理器，其中协处理器包括：存储外部给定操作模式的参数寄存器和生成多项式的设置; 以及计算电路，其基于操作模式和生成多项式操作，并且以并行方式通过每个周期的多个位执行编码和解码处理所需的计算，并且协处理器还包括存储器 控制器，包括：用于输出存储设备的地址的地址发生器电路; 用于临时存储数据的FIFO电路; 以及用于构成用于输出的预定数量的数据位的数据打包电路。

公开(公告)号：US08734037B2

公开(公告)日：2014-05-27

申请号：US12949497

申请日：2010-11-18

Applicant: Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Kengo Nieda ,  Tetsuhiro Nitta

Inventor： Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Kengo Nieda ,  Tetsuhiro Nitta

IPC: B41J15/00 ,  B41J2/165 ,  B65H85/00

CPC classification number: B41J11/008 ,  B41J11/0095 ,  B41J13/0009

Abstract: An apparatus may include a print head, multiple roller pairs to convey a sheet, a direct sensor, and a control unit. The print head prints on a conveyed sheet. The multiple roller pairs nip the sheet at an upstream side of the print head to convey the sheet, nip the sheet at a downstream side of the print head, and nip the sheet at an upstream side of a first roller pair to convey the sheet. The direct sensor measures a surface of the conveyed sheet at a measurement position between a nip position of the first roller pair and a nip position of a third roller pair to obtain information relating to a movement state of the sheet. The control unit controls to correct at least one of driving control of the print head and conveying control of the sheet, based on the information obtained by the direct sensor.

Abstract translation: 装置可以包括打印头，用于传送片材的多个辊对，直接传感器和控制单元。 打印头打印在传送的纸张上。 多个辊对在打印头的上游侧夹持纸张以输送纸张，在打印头的下游侧夹持纸张，并且将纸张夹在第一辊对的上游侧以输送纸张。 直接传感器在第一辊对的夹持位置和第三辊对的夹持位置之间的测量位置处测量传送的纸张的表面，以获得与纸张的移动状态有关的信息。 控制单元基于由直接传感器获得的信息来控制打印头的驱动控制和纸张的传送控制中的至少一个。

公开(公告)号：US20130318329A1

公开(公告)日：2013-11-28

申请号：US13982526

申请日：2011-09-15

Applicant: Toshiki Takeuchi ,  Hiroyuki Igura

Inventor： Toshiki Takeuchi ,  Hiroyuki Igura

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/57 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3877 ,  H04B1/7115

Abstract: In order to enable to quickly and efficiently execute, by one system, various modulation/demodulation/synchronous processes in a plurality of radio communication methods, a co-processor (22) for complex arithmetic processing, which forms a processor system (100), includes a complex arithmetic circuit (22) that executes for complex data a complex arithmetic operation required for radio communication in accordance with an instruction from a primary processor (10), and a memory controller (20, 21) that operates in parallel with the complex arithmetic circuit and accesses a memory. A trace circuit provided in the complex arithmetic circuit (22) monitors arithmetic result data for first complex data series sequentially read from the memory, and detects a normalization coefficient for normalizing the arithmetic result data.

Abstract translation: 为了能够通过一个系统快速有效地执行多个无线电通信方法中的各种调制/解调/同步过程，用于形成处理器系统（100）的用于复杂运算处理的协处理器（22） 包括：复数运算电路（22），用于根据来自主处理器（10）的指令对复数数据执行无线电通信所需的复杂算术运算，以及存储器控制器（20,21），其与所述复合体并行操作 算术电路并访问存储器。 在复数运算电路（22）中提供的跟踪电路监视从存储器顺序读取的第一复数数据序列的运算结果数据，并检测归一化系数以归一化运算结果数据。

公开(公告)号：US08485630B2

公开(公告)日：2013-07-16

申请号：US12945598

申请日：2010-11-12

Applicant: Koichiro Kawaguchi ,  Yasuhiko Ikeda ,  Toshiki Takeuchi ,  Kengo Nieda ,  Masahito Yoshida ,  Masato Izumi ,  Kenji Shigeno ,  Ryosuke Sato ,  Noriyuki Sugiyama ,  Takaaki Ishida

Inventor： Koichiro Kawaguchi ,  Yasuhiko Ikeda ,  Toshiki Takeuchi ,  Kengo Nieda ,  Masahito Yoshida ,  Masato Izumi ,  Kenji Shigeno ,  Ryosuke Sato ,  Noriyuki Sugiyama ,  Takaaki Ishida

IPC: B41J29/38

CPC classification number: B65H23/038 ,  B65H2301/515 ,  B65H2404/15212

Abstract: A device includes a conveying roller configured to convey a recording medium, a follower roller configured to press the recording medium against the conveying roller, a detector configured to detect a direction of skew of the conveyed recording medium, and a changer configured to change a state of contact between the recording medium and the conveying roller in accordance with a result of the detection by the detector such that a length of a portion of the conveying roller that is in contact with the recording medium in a conveyance direction is larger on a side toward which the recording medium is skewed than on an opposite side.

Abstract translation: 一种装置，包括构造成传送记录介质的输送辊，被配置为将记录介质压靠在输送辊上的从动辊，配置成检测所传送的记录介质的歪斜方向的检测器，以及改变状态 根据检测器的检测结果，记录介质和输送辊之间的接触的距离使得在输送方向上与记录介质接触的输送辊的一部分的长度在朝向 记录介质的倾斜度大于相对侧。

公开(公告)号：US20130067201A1

公开(公告)日：2013-03-14

申请号：US13637776

申请日：2011-05-24

Applicant: Toshiki Takeuchi ,  Hiroyuki Igura

Inventor： Toshiki Takeuchi ,  Hiroyuki Igura

IPC: G06F9/30

CPC classification number: G06F15/17337

Abstract: The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determines whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.

Abstract translation: 多处理器系统包括一个或多个主处理器和多个子处理器，以及执行控制电路，其执行每个子处理器的执行控制，其中执行控制电路包括用于执行控制处理的执行控制处理器 每个子处理器，用于激活每个子处理器的命令的控制总线输出单元，用于来自每个子处理器的状态通知的状态总线输入单元，确定状态通知是否具有 一个一对一的依赖关系，一个接下来要在操作序列上发出的处理命令，并且要高速处理的状态加速器，当高速处理状态通知时发出相应的处理激活命令 以及状态FIFO控制单元，其通过使用执行控制处理器来处理状态通知。

公开(公告)号：US08393705B2

公开(公告)日：2013-03-12

申请号：US12950594

申请日：2010-11-19

Applicant: Kenji Shigeno ,  Yasuhiko Ikeda ,  Masahito Yoshida ,  Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Masato Izumi ,  Ryosuke Sato ,  Kengo Nieda

Inventor： Kenji Shigeno ,  Yasuhiko Ikeda ,  Masahito Yoshida ,  Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Masato Izumi ,  Ryosuke Sato ,  Kengo Nieda

IPC: B41J29/38

CPC classification number: B41J11/42 ,  B41J11/0025 ,  B41J15/04 ,  B65H29/008 ,  B65H2301/12 ,  B65H2403/942

Abstract: An apparatus includes a line-type recording head including a plurality of recording elements formed thereon, a holding unit configured to hold a sheet, a conveyance mechanism configured to convey the sheet held by the holding unit to a position of recording by the recording head, a shift mechanism capable of relatively shifting a position of the sheet in a sheet width direction with respect to the recording head while the sheet is fed from the holding unit to the recording position, and a control unit configured to control the conveyance mechanism and the shift mechanism.

Abstract translation: 一种装置，包括：线形记录头，包括形成在其上的多个记录元件;保持单元，被构造成保持片材;输送机构，其构造成将由所述保持单元保持的片材输送到由所述记录头记录的位置; 一种移动机构，其能够在从所述保持单元向所述记录位置供给所述纸张的同时相对于所述记录头在纸张宽度方向上相对移动所述纸张的位置;以及控制单元，其被配置为控制所述输送机构和所述移动 机制。

公开(公告)号：US20120246369A1

公开(公告)日：2012-09-27

申请号：US13511559

申请日：2010-11-24

Applicant: Toshiki Takeuchi

Inventor： Toshiki Takeuchi

IPC: G06F13/40

CPC classification number: G06F11/3027 ,  G06F11/3089

Abstract: A bus monitor circuit that produces a bus monitor output signal on a bus transmitting data between a master and a slave includes an access information/write data FIFO and a read data FIFO. When an attribute of the access information stored at a header of the access information/write data FIFO indicates a write access, it directly outputs a bus monitor output signal indicating access information accompanied with the corresponding write data which is transmitted in the same cycle. When an attribute of the access information stored at the header of the access information/write data FIFO indicates a read access, it waits for the read data FIFO storing the corresponding read data, and then outputs a bus monitor output signal indicating the access information paired with the read data in the same cycle. Thus, it is possible to guarantee the occurrence order of bus access according to a bus interface protocol enabling pipeline transaction, thus outputting a bus monitor output signal indicating a pair of access information and data information.

Abstract translation: 总线监视器电路在母线和从机之间的总线上产生总线监视器输出信号，包括访问信息/写数据FIFO和读数据FIFO。 存储在访问信息/写入数据FIFO的头部的访问信息的属性表示写入访问时，直接输出指示伴随着在相同周期中发送的相应写入数据的访问信息的总线监视器输出信号。 存储在访问信息/写入数据FIFO的头部的访问信息的属性指示读取访问时，等待读取数据FIFO存储对应的读取数据，然后输出表示访问信息配对的总线监视器输出信号 读取数据在同一周期。 因此，可以根据总线接口协议保证总线访问的发生顺序，从而能够进行流水线交易，从而输出指示一对访问信息和数据信息的总线监视器输出信号。

公开(公告)号：US20120098190A1

公开(公告)日：2012-04-26

申请号：US12965787

申请日：2010-12-10

Applicant: Kengo Nieda ,  Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Ryosuke Sato ,  Shigeru Toriihara

Inventor： Kengo Nieda ,  Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Ryosuke Sato ,  Shigeru Toriihara

IPC: B65H7/02 ,  B65H5/36 ,  B65H5/06

CPC classification number: B65H9/00 ,  B41J11/0045 ,  B65H23/025 ,  B65H2220/09 ,  B65H2301/51256 ,  B65H2404/14 ,  B65H2404/1431 ,  B65H2801/06

Abstract: A sheet conveyance apparatus includes: a guide unit for guiding the side end of the sheet; a first roller pair arranged on the downstream side of the guide unit for conveying the sheet, including a driven roller held in contact with a whole sheet in a sheet width direction; and a second roller pair having a conveyance roller arranged on the downstream side of the roller and adapted to convey the sheet, and a plurality of pinch rollers pinching the sheet in cooperation with the conveyance roller, wherein each of the plurality of pinch rollers applies to the sheet a conveyance force inclined toward a conveyance path side end, which is nearer to the pinch roller, and wherein the smaller the distance between the pinch roller and the conveyance path side end, the greater the inclination of the conveyance force thereof.

公开(公告)号：US08152269B2

公开(公告)日：2012-04-10

申请号：US12540833

申请日：2009-08-13

Applicant: Toshiki Takeuchi ,  Nobuhiro Toki ,  Haruo Uchida

Inventor： Toshiki Takeuchi ,  Nobuhiro Toki ,  Haruo Uchida

IPC: B41J2/165 ,  B41J23/04 ,  B41J23/08 ,  B41J23/14

CPC classification number: B41J23/025 ,  B41J2/16532 ,  B41J29/02 ,  B41J29/38 ,  Y10T74/20104

Abstract: A recording apparatus includes a carriage carrying a recording head and being movably supported, the recording head being configured to eject liquid onto a recording medium, a plurality of driven units to be driven by a drive source that generates a driving force, a transmission-switching mechanism configured to switch between the driven units, a carriage locker configured to prevent and allow movement of the carriage, and a transmission-switching locker configured to prevent and allow switching between the driven units. Movement prevention by the carriage locker and switching prevention by the transmission-switching locker are in synchronicity, and movement allowance by the carriage locker and switching allowance by the transmission-switching locker are in synchronicity.

Abstract translation: 记录装置包括承载记录头并被可移动地支撑的托架，记录头被配置为将液体喷射到记录介质上，多个被驱动单元由驱动源驱动以产生驱动力，传输切换 被配置为在被驱动单元之间切换的机构，构造成防止和允许滑架移动的滑架锁定装置，以及配置成防止和允许从动单元之间切换的传动切换锁。 车厢储物柜的防止动作和防止变速箱切换的交换机处于同步状态，车厢储物柜的移动余量和变速箱切换储物柜的切换余量是同步的。