公开(公告)号：US5497120A

公开(公告)日：1996-03-05

申请号：US350030

申请日：1994-11-29

申请人： Masao Ito ,  Takahiro Miki

发明人： Masao Ito ,  Takahiro Miki

IPC分类号： G01R19/165 ,  H03F1/30 ,  H03F3/45 ,  H03K17/16

CPC分类号： G01R19/16519 ,  H03F1/303 ,  H03F3/45076

摘要： A differential amplifier circuit is obtained in which an operating power source voltage is suppressed to a minimum necessary level. The differential amplifier circuit includes a bias circuit having a differential amplifier with NMOS transistors (11A, 11B, 12A and 12B) and PMOS transistors (13A and 13B). Sources of NMOS transistors (11A)and (11B) are commonly grounded. A bias voltage (VB1) is supplied to gates of the NMOS transistors (11A) and (11B). Drains of the NMOS transistors (11A) and (11B) are connected to sources of NMOS transistors (12A) and (12B), respectively. A gate and a drain of the NMOS transistor (12A) are short-circuited to each other with the drain connected to a drain of a PMOS transistor (13A). A bias voltage (VB4) is applied to a gate of the NMOS transistor (12B). A drain of the NMOS transistor (12B) is connected to a drain of the PMOS transistor (13B) whose gate and drain are shared by each other. Gates of the PMOS transistors (13A) and (13B) are connected to a bias terminal (72) while sources of the PMOS transistors (13A) and (13B) are commonly connected to a power source. The bias terminal (72) is connected to an input bias terminal of a differential amplifier.

摘要翻译： 获得了将工作电源电压抑制到最小必要水平的差分放大电路。 差分放大器电路包括具有NMOS晶体管（11A，11B，12A和12B）和PMOS晶体管（13A和13B）的差分放大器的偏置电路。 NMOS晶体管（11A）和（11B）的源极通常接地。 偏置电压（VB1）被提供给NMOS晶体管（11A）和（11B）的栅极。 NMOS晶体管（11A）和（11B）的漏极分别连接到NMOS晶体管（12A）和（12B）的源极。 NMOS晶体管（12A）的栅极和漏极彼此短路，漏极连接到PMOS晶体管（13A）的漏极。 偏置电压（VB4）施加到NMOS晶体管（12B）的栅极。 NMOS晶体管（12B）的漏极连接到其栅极和漏极彼此共享的PMOS晶体管（13B）的漏极。 PMOS晶体管（13A）和（13B）的栅极连接到偏置端子（72），而PMOS晶体管（13A）和（13B）的源极共同连接到电源。 偏置端子（72）连接到差分放大器的输入偏置端子。

公开(公告)号：US5225837A

公开(公告)日：1993-07-06

申请号：US706834

申请日：1991-05-29

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/36 ,  H03M1/78

CPC分类号： H03M1/362

摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.

摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器 的电平检测器。 电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。 电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述 第一参考电压和所述第二参考电压。 比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。 该结构实现了具有较低元件精度的A / D转换器。

公开(公告)号：US5315301A

公开(公告)日：1994-05-24

申请号：US976056

申请日：1992-11-13

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0643 ,  H03M1/068 ,  H03M1/361

摘要： An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

摘要翻译： 公开了一种改进的并行型A / D转换器，其包括由伪NMOS型ROM构成的编码器3和由伪PMOS型ROM构成的编码器28。 这些编码器连接到预编码器2的输出。平均电路29接收从两个编码器提供的二进制数据，以将它们的平均值数据提供为转换的二进制输出数据。 即使在多寻址的情况下，平均电路也可以提供作为转换数据的正确数据。 结果，已经获得了不受噪声等影响的A / D转换器。

公开(公告)号：US09564805B2

公开(公告)日：2017-02-07

申请号：US14009715

申请日：2012-04-09

申请人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

发明人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

IPC分类号： H02M3/158 ,  G05F3/30 ,  G05F3/26

CPC分类号： G05F3/267 ,  G05F3/20 ,  G05F3/26 ,  G05F3/30 ,  H02M3/158

摘要： A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.

摘要翻译： 其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管（Q1，Q2）。 Q1的基极端子设置在Q2的集电极侧。 第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件（R1）将Q1的集电极侧连接到R2。 第三电阻元件（R3）将Q2的基极端子与发射极端子的电位相连。 放大器（A1）输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部（MP1，MP2）将放大器输出转换为R1和R2的连接节点的电流。 然后基于所产生的电流输出电压。

公开(公告)号：US07295067B2

公开(公告)日：2007-11-13

申请号：US11181891

申请日：2005-07-15

申请人： Masaomi Kamakura ,  Takahiro Miki

发明人： Masaomi Kamakura ,  Takahiro Miki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45644

摘要： A current source block and a negative resistance generation block are connected in parallel. The negative resistance generation block generates a negative resistance in response to the minute variations of an output voltage. Thus the output resistance of a current source circuit is given by the combined resistance of the negative resistance and the resistance of a resistor in the current source block connected in parallel. The resistance of the resistor in the current source block and the negative resistance are controlled to be substantially the same to thereby increase the output resistance of the current source circuit. The current source circuit serves to increase an output resistance when viewed from an differential output terminal. As a result, use of this current source circuit realizes a differential amplifier providing a high gain.

摘要翻译： 电流源块和负电阻生成块并联连接。 负电阻产生块响应于输出电压的微小变化而产生负电阻。 因此，电流源电路的输出电阻由负电阻的组合电阻和并联连接的电流源模块中的电阻器的电阻给出。 电流源电阻中的电阻和负电阻的电阻被控制为基本相同，从而增加电流源电路的输出电阻。 电流源电路用于当从差分输出端子观察时增加输出电阻。 结果，使用该电流源电路实现提供高增益的差分放大器。

公开(公告)号：US07053810B2

公开(公告)日：2006-05-30

申请号：US11151551

申请日：2005-06-14

申请人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

发明人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

IPC分类号： H03M1/34

CPC分类号： H03M1/1225 ,  H03M1/46

摘要： A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

摘要翻译： 逐次逼近A / D转换器包括第一和第二S / H，并且比较器同时采样并保持第一和第二外部模拟输入电压，并将保持的，第一和第二外部模拟输入电压与参考电压进行比较，以输出具有 对应于所得到的比较的电平，以及响应于第一和第二信号而工作以产生参考电压的参考电压发生器。 两个S / H和比较器共享单个参考电压发生器。 可以实现减少的芯片面积。

公开(公告)号：US20060044169A1

公开(公告)日：2006-03-02

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage—OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于在接近ON控制电压（BIAS2）的电压下关断NMOS晶体管M12P，M12N，M22P，M22N，M32P和M32N的OFF控制电压（BIAS3）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US06472930B1

公开(公告)日：2002-10-29

申请号：US09177503

申请日：1998-10-23

申请人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

IPC分类号： G05F110

CPC分类号： G05F3/24

摘要： A current generator (CG) is composed of a constant-current-source transistor M1, and transistors (M2, M3). On receipt of control signals (VG2, VG3) respectively from a driver circuit (not shown), the transistors (M2, M3) complementarily operate to function as current switches. Then, damping resistance (R3) is provided between the drain electrode of the transistor (M3) and an output terminal ({overscore (IT)}). The output terminal ({overscore (IT)}) is connected to a ground (GND), while an output terminal (IT) is grounded via an external terminal (R2). Such a structure allows a semiconductor integrated circuit device to reduce its output ringing and further to suppress imperfections resulting from the adoption of the structure to reduce the ringing.

摘要翻译： 电流发生器（CG）由恒流源晶体管M1和晶体管（M2，M3）组成。 分别从驱动电路（未示出）接收到控制信号（VG2，VG3）时，晶体管（M2，M3）互补地工作，起到电流开关的作用。 然后，在晶体管（M3）的漏电极和输出端（{overscore（IT）}之间设置阻尼电阻（R3）。 输出端子（{overscore（IT）}）连接到地（GND），而输出端（IT）通过外部端子（R2）接地。 这种结构允许半导体集成电路器件减少其输出振铃并且进一步抑制由采用该结构导致的减少振铃的缺陷。

公开(公告)号：US06388502B2

公开(公告)日：2002-05-14

申请号：US09756215

申请日：2001-01-09

申请人： Kazuo Kaneki ,  Takahiro Miki

发明人： Kazuo Kaneki ,  Takahiro Miki

IPC分类号： G06F744

CPC分类号： H03F3/45089 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0088 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45631 ,  H03F2203/45702 ,  H03F2203/45722

摘要： An output signal gain is improved by a semiconductor integrated circuit comprising a mixer circuit having an upper-stage transistor circuit to which a local signal is inputted and a lower-stage transistor circuit to which an RF signal is inputted, wherein a first resistance and a second resistance serving as a load are connected between the upper-stage transistor circuit and supply voltage, and a result of multiplication operation performed via the upper-stage transistor circuit and the lower-stage transistor circuit is made to appear as a first signal and a second signal at the first resistance and the second resistance respectively on the basis of the supply voltage; an emitter follower circuit including a first transistor and a second transistor for respectively receiving outputs from the first resistance and the second resistance and outputting a first amplified signal and a second amplified signal that have been subjected to impedance conversion on the basis of the supply voltage; and an operational amplifier circuit for receiving the first amplified signal on an inverting input side via an input resistance and the second amplified signal on a non-inverting input side, the operational amplifier circuit including a feedback resistance for connecting its output side and the inverting input side provided with the input resistance.

摘要翻译： 输出信号增益由包括具有输入本地信号的上级晶体管电路的混频器电路和输入RF信号的下级晶体管电路的半导体集成电路改进，其中第一电阻和 作为负载的第二电阻连接在上级晶体管电路和电源电压之间，并且经由上级晶体管电路和下级晶体管电路执行的乘法运算的结果作为第一信号和 第二电阻和第二电阻分别基于电源电压; 射极跟随器电路，包括第一晶体管和第二晶体管，用于分别从第一电阻和第二电阻接收输出，并输出基于电源电压进行阻抗转换的第一放大信号和第二放大信号; 以及运算放大器电路，用于经由输入电阻在反相输入侧接收第一放大信号，并且在非反相输入侧接收第二放大信号，运算放大器电路包括用于连接其输出侧和反相输入端的反馈电阻 一侧设有输入电阻。

公开(公告)号：US06380881B2

公开(公告)日：2002-04-30

申请号：US09757462

申请日：2001-01-11

申请人： Hisashi Harada ,  Takahiro Miki

发明人： Hisashi Harada ,  Takahiro Miki

IPC分类号： H03M106

CPC分类号： H03M1/0695 ,  H03M1/46

摘要： A successive approximation A/D converter includes a comparator formed of a plurality of comparators and comparing an analog input voltage with a plurality of voltages output from a digital-to-analog converter so as to output a conversion result including at least 2 bits. A control circuit in the A/D converter performs error correction based on the final result output from the comparator and outputs a final conversion result to a conversion result output terminal.

摘要翻译： 逐次逼近A / D转换器包括由多个比较器形成的比较器，并将模拟输入电压与从数模转换器输出的多个电压进行比较，以便输出包括至少2位的转换结果。 A / D转换器中的控制电路根据比较器的最终结果输出执行纠错，并向转换结果输出端输出最终转换结果。